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S71PL254/127/064/032J based MCPs
Stacked Multi-Chip Product (MCP) Flash Memory and RAM 256M/128/64/32 Megabit (16/8/4/2M x 16-bit) CMOS 3.0 Volt-only Simultaneous Operation Page Mode Flash Memory and 64/32/16/8/4 Megabit (4M/2M/1M/512K/256K x 16-bit) Static RAM/Pseudo Static RAM Datasheet Distinctive Characteristics
MCP Features
Power supply voltage of 2.7 to 3.1 volt High performance -- 55 ns -- 65 ns (65 ns Flash, 70ns pSRAM) Packages -- 7 x 9 x 1.2mm 56 ball FBGA -- 8 x 11.6 x 1.2mm 64 ball FBGA -- 8 x 11.6 x 1.4mm 84 ball FBGA Operating Temperature -- -25C to +85C -- -40C to +85C
ADVANCE
General Description
The S71PL series is a product line of stacked Multi-Chip Product (MCP) packages and consists of: One or more S29PL (Simultaneous Read/Write) Flash memory die pSRAM or SRAM The 256Mb Flash memory consists of two S29PL127J devices. In this case, CE#f2 is used to access the second Flash and no extra address lines are required. The products covered by this document are listed in the table below: Flash Memory Density 32Mb 4Mb 8Mb pSRAM Density 16Mb 32Mb 64Mb S71PL032J40 S71PL032J80 S71PL032JA0 S71PL064J80 S71PL064JA0 S71PL064JB0 S71PL127JA0 S71PL127JB0 S71PL127JC0 S71PL254JB0 S71PL254JC0 64Mb 128Mb 256Mb
Flash Memory Density 32Mb SRAM Density (Note) 4Mb 8Mb S71PL032J04 S71PL032J08 S71PL064J08 64Mb
Note: Not recommended for new designs; use pSRAM based MCPs instead.
Publication Number S71PL254/127/064/032J_00
Revision A
Amendment 6
Issue Date November 22, 2004
Preliminary
Product Selector Guide
32Mb Flash Memory
Device-Model# S71PL032J04-0B S71PL032J04-0F S71PL032J04-0K S71PL032J40-0K S71PL032J40-07 S71PL032J08-0B S71PL032J80-0P S71PL032J80-07 S71PL032JA0-0K S71PL032JA0-0F S71PL032JA0-0Z Flash Access time (ns) 65 65 65 65 65 65 65 65 65 65 65 (p)SRAM density 4M SRAM 4M SRAM 4M SRAM 4M pSRAM 4M pSRAM 8M SRAM 8M pSRAM 8M pSRAM 16Mb pSRAM 16Mb pSRAM 32M pSRAM (p)SRAM Access time (ns) pSRAM type 70 70 70 70 70 70 70 70 70 70 70 SRAM2 SRAM3 SRAM4 pSRAM4 pSRAM1 SRAM2 pSRAM5 pSRAM1 pSRAM1 pSRAM3 pSRAM7 Package TSC056 TSC056 TSC056 TLC056 TSC056 TSC056 TSC056 TSC056 TSC056 TSC056 TLC056
64Mb Flash Memory
Device-Model# S71PL064J08-0B S71PL064J08-0U S71PL064J80-0K S71PL064J80-07 S71PL064J80-0P S71PL064JA0-0Z S71PL064JA0-0B S71PL064JA0-07 S71PL064JA0-0P S71PL064JB0-07 S71PL064JB0-0B S71PL064JB0-0U Flash Access time (ns) 65 65 65 65 65 65 65 65 65 65 65 65 (p)SRAM density 8M SRAM 8M SRAM 8M pSRAM 8M pSRAM 8M pSRAM 16M pSRAM 16M pSRAM 16M pSRAM 16M pSRAM 32M pSRAM 32M pSRAM 32M pSRAM (p)SRAM Access time (ns) 70 70 70 70 70 70 70 70 70 70 70 70 (p)SRAM type SRAM2 SRAM4 pSRAM1 pSRAM1 pSRAM5 pSRAM7 SRAM3 pSRAM1 pSRAM7 pSRAM1 pSRAM2 pSRAM6 Package TLC056 TLC056 TSC056 TLC056 TSC056 TLC056 TLC056 TLC056 TLC056 TLC056 TLC056 TLC056
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S71PL254/127/064/032J based MCPs
S71PL254/127/064/032J_00_A6 November 22, 2004
Preliminary
128Mb Flash Memory
Device-Model# S71PL127JA0-9P S71PL127JA0-9Z S71PL127JA0-97 S71PL127JB0-97 S71PL127JB0-9Z S71PL127JB0-9U S71PL127JB0-9B S71PL127JC0-97 S71PL127JC0-9Z S71PL127JC0-9U Flash Access time (ns) 65 65 65 65 65 65 65 65 65 65 pSRAM density 16M pSRAM 16M pSRAM 16M pSRAM 32M pSRAM 32M pSRAM 32M pSRAM 32M pSRAM 64M pSRAM 64M pSRAM 64M pSRAM pSRAM Access time (ns) 70 70 70 70 70 70 70 70 70 70 pSRAM type pSRAM7 pSRAM7 pSRAM1 pSRAM1 pSRAM7 pSRAM6 pSRAM2 pSRAM1 pSRAM7 pSRAM6 Package TLA064 TLA064 TLA064 TLA064 TLA064 TLA064 TLA064 TLA064 TLA064 TLA064
256Mb Flash Memory (2xS29PL127J)
Device-Model# S71PL254JB0-T7 S71PL254JB0-TB S71PL254JB0-TU S71PL254JC0-TB S71PL254JC0-TZ Flash Access time (ns) 65 65 65 65 65 pSRAM density 32M pSRAM 32M pSRAM 32M pSRAM 64M pSRAM 64M pSRAM pSRAM Access time (ns) 70 70 70 70 70 pSRAM type pSRAM1 pSRAM2 pSRAM6 pSRAM2 pSRAM7 Package FTA084 FTA084 FTA084 FTA084 FTA084
November 22, 2004 S71PL254/127/064/032J_00_A6
S71PL254/127/064/032J based MCPs
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Advance
Information
S71PL254/127/064/032J based MCPs
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ........................................................................................................ 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
32Mb Flash Memory .............................................................................................2 64Mb Flash Memory .............................................................................................2 128Mb Flash Memory ...........................................................................................3 256Mb Flash Memory (2xS29PL127J) ...............................................................3
Table 8. Autoselect Codes (High Voltage Method) .................. 49 Table 9. PL127J Boot Sector/Sector Block Addresses for Protection/ Unprotection ..................................................................... 50 Table 10. PL064J Boot Sector/Sector Block Addresses for Protection/Unprotection ...................................................... 51 Table 11. PL032J Boot Sector/Sector Block Addresses for Protection/Unprotection ...................................................... 52
Selecting a Sector Protection Mode ............................................................. 52
Table 12. Sector Protection Schemes ................................... 53
Connection Diagram (S71PL032J) Connection Diagram (S71PL064J) Connection Diagram (S71PL127J) Connection Diagram (S71PL254J)
. . . . . . . . . . . . . .9 . . . . . . . . . . . . . 10 . . . . . . . . . . . . . 11 . . . . . . . . . . . . . 12
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 53 Sector Protection Schemes . . . . . . . . . . . . . . . . . 53
Password Sector Protection ........................................................................... 53 WP# Hardware Protection ............................................................................. 53 Selecting a Sector Protection Mode ............................................................. 53
Special Handling Instructions For FBGA Package ................................. 12
Persistent Sector Protection . . . . . . . . . . . . . . . . 54
Persistent Protection Bit (PPB) ...................................................................... 54 Persistent Protection Bit Lock (PPB Lock) ................................................. 54 Persistent Sector Protection Mode Locking Bit ....................................... 56
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 14 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . .20
TLC056--56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7mm Package ................................................................................................ 20 TSC056--56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7mm Package ................................................................................................. 21 TLA064--64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6mm Package ............................................................................................ 22 TSB064--64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package ...........................................................................................23 FTA084--84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6mm ............................................................................................................ 24
Password Protection Mode . . . . . . . . . . . . . . . . . 56
Password and Password Mode Locking Bit ................................................ 56 64-bit Password .................................................................................................. 57 Write Protect (WP#) ....................................................................................... 57 Persistent Protection Bit Lock ................................................................... 57 High Voltage Sector Protection .....................................................................58
Figure 1. In-System Sector Protection/Sector Unprotection Algorithms........................................................................ 59
Temporary Sector Unprotect ........................................................................60
Figure 2. Temporary Sector Unprotect Operation ................... 60
S29PL127J/S29PL064J/S29PL032J for MCP
General Description . . . . . . . . . . . . . . . . . . . . . . . 27
Simultaneous Read/Write Operation with Zero Latency ......................27 Page Mode Features ...........................................................................................27 Standard Flash Memory Features ...................................................................27
Secured Silicon Sector Flash Memory Region ...........................................60 Factory-Locked Area (64 words) ...............................................................61 Customer-Lockable Area (64 words) .......................................................61 Secured Silicon Sector Protection Bits .....................................................61
Figure 3. Secured Silicon Sector Protect Verify ...................... 62
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .29 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Simultaneous Read/Write Block Diagram . . . . . . 31 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 33
Table 1. PL127J Device Bus Operations ................................ 33
Hardware Data Protection .............................................................................62 Low VCC Write Inhibit ................................................................................62 Write Pulse "Glitch" Protection ...............................................................62 Logical Inhibit ...................................................................................................62 Power-Up Write Inhibit ...............................................................................62
Common Flash Memory Interface (CFI) . . . . . . 63
Table 13. CFI Query Identification String .............................. 63 Table 14. System Interface String ........................................ 64 Table 15. Device Geometry Definition ................................... 64 Table 16. Primary Vendor-Specific Extended Query ................ 65
Command Definitions . . . . . . . . . . . . . . . . . . . . . 66
Reading Array Data ...........................................................................................66 Reset Command .................................................................................................66 Autoselect Command Sequence .................................................................... 67 Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence .................................................................................................................... 67 Word Program Command Sequence ........................................................... 67 Unlock Bypass Command Sequence ........................................................68
Figure 4. Program Operation ............................................... 69
Requirements for Reading Array Data .........................................................33 Random Read (Non-Page Read) ................................................................33 Page Mode Read ..............................................................................................34
Table 2. Page Select .......................................................... 34
Simultaneous Read/Write Operation ...........................................................34
Table 3. Bank Select .......................................................... 34
Writing Commands/Command Sequences .................................................35 Accelerated Program Operation ...............................................................35 Autoselect Functions .....................................................................................35 Standby Mode .......................................................................................................35 Automatic Sleep Mode ......................................................................................36 RESET#: Hardware Reset Pin .........................................................................36
Table 4. PL127J Sector Architecture ..................................... 37 Table 5. PL064J Sector Architecture ..................................... 44 Table 6. PL032J Sector Architecture ..................................... 47 Table 7. Secured Silicon Sector Addresses ............................ 48
Chip Erase Command Sequence ...................................................................69 Sector Erase Command Sequence ................................................................70
Figure 5. Erase Operation ................................................... 71
Erase Suspend/Erase Resume Commands ................................................... 71 Command Definitions Tables ......................................................................... 72
Table 17. Memory Array Command Definitions ...................... 72 Table 18. Sector Protection Command Definitions .................. 73
Write Operation Status . . . . . . . . . . . . . . . . . . . . 74
DQ7: Data# Polling ............................................................................................ 75
Autoselect Mode ................................................................................................ 49
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Figure 6. Data# Polling Algorithm......................................... 76
RY/BY#: Ready/Busy# .......................................................................................76 DQ6: Toggle Bit I ................................................................................................76
Figure 7. Toggle Bit Algorithm.............................................. 78
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 99
Power Up ..............................................................................................................99
Figure 23. Power Up 1 (CS1# Controlled) ............................. 99 Figure 24. Power Up 2 (CS2 Controlled)................................ 99
DQ2: Toggle Bit II .............................................................................................. 78 Reading Toggle Bits DQ6/DQ2 ..................................................................... 78 DQ5: Exceeded Timing Limits ........................................................................79 DQ3: Sector Erase Timer .................................................................................79
Table 19. Write Operation Status ......................................... 80
Functional Description . . . . . . . . . . . . . . . . . . . . . 100 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 100 DC Recommended Operating Conditions . . . . . 100 DC and Operating Characteristics . . . . . . . . . . . 101
Common ...............................................................................................................101 16M pSRAM ..........................................................................................................102 32M pSRAM .........................................................................................................102 64M pSRAM .........................................................................................................103
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . 81
Figure 8. Maximum Overshoot Waveforms............................. 81
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .82
Industrial (I) Devices ......................................................................................... 82 Wireless Devices ............................................................................................... 82 Supply Voltages ................................................................................................... 82
AC Operating Conditions . . . . . . . . . . . . . . . . . . 103
Test Conditions (Test Load and Test Input/Output Reference) ........103
Figure 25. Output Load .................................................... 103
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .83
Table 20. CMOS Compatible ................................................ 83
AC Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . .84
Test Conditions .................................................................................................. 84
Figure 9. Test Setups......................................................... 84 Table 21. Test Specifications ............................................... 84
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 105
Read Timings .......................................................................................................105
Figure 26. Timing Waveform of Read Cycle(1) ..................... 105 Figure 27. Timing Waveform of Read Cycle(2) ..................... 105 Figure 28. Timing Waveform of Read Cycle(2) ..................... 105
ACC Characteristics (Ta = -40C to 85C, VCC = 2.7 to 3.1 V) ........104
Switching Waveforms ....................................................................................... 85
Table 22. Key to Switching Waveforms ................................. 85 Figure 10. Input Waveforms and Measurement Levels............. 85
Write Timings .....................................................................................................106
Figure 29. Write Cycle #1 (WE# Controlled)........................ Figure 30. Write Cycle #2 (CS1# Controlled) ...................... Figure 31. Timing Waveform of Write Cycle(3) (CS2 Controlled) ............................................................. Figure 32. Timing Waveform of Write Cycle(4) (UB#, LB# Controlled) ..................................................................... 106 106 107 107
VCC RampRate .................................................................................................. 85 Read Operations ................................................................................................ 86
Table 23. Read-Only Operations .......................................... 86 Figure 11. Read Operation Timings ....................................... 86 Figure 12. Page Read Operation Timings ............................... 87
Reset ...................................................................................................................... 87
Table 24. Hardware Reset (RESET#) .................................... 87 Figure 13. Reset Timings..................................................... 88
pSRAM Type 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 109 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 30. DC Recommended Operating Conditions ............... 109 Table 31. DC Characteristics (TA = -25C to 85C, VDD = 2.6 to 3.3V) ............................................................................. 110
Erase/Program Operations ............................................................................. 89
Table 25. Erase and Program Operations .............................. 89
Timing Diagrams ................................................................................................. 90
Figure 14. Program Operation Timings .................................. 90 Figure 15. Accelerated Program Timing Diagram .................... 90 Figure 16. Chip/Sector Erase Operation Timings ..................... 91 Figure 17. Back-to-back Read/Write Cycle Timings ................. 91 Figure 18. Data# Polling Timings (During Embedded Algorithms) ............................................ 92 Figure 19. Toggle Bit Timings (During Embedded Algorithms) .. 92 Figure 20. DQ2 vs. DQ6 ...................................................... 93
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 32. AC Characteristics and Operating Conditions (TA = -25C to 85C, VDD = 2.6 to 3.3V) .............................................. 110 Table 33. AC Test Conditions ............................................. 111 Figure 33. AC Test Loads .................................................. 111 Figure 34. State Diagram ................................................. 112 Table 34. Standby Mode Characteristics .............................. 112
Protect/Unprotect . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 26. Temporary Sector Unprotect ................................. 93 Figure 21. Temporary Sector Unprotect Timing Diagram.......... 93 Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram............................................................................ 94
Controlled Erase Operations ..........................................................................95
Table 27. Alternate CE# Controlled Erase and Program Operations ........................................................... 95 Table 28. Alternate CE# Controlled Write (Erase/Program) Operation Timings ............................................................. 96 Table 29. Erase And Programming Performance .................... 97
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 35. Read Cycle 1--Addressed Controlled ................... Figure 36. Read Cycle 2--CS1# Controlled.......................... Figure 37. Write Cycle 1--WE# Controlled .......................... Figure 38. Write Cycle 2--CS1# Controlled ......................... Figure 39. Write Cycle3--UB#, LB# Controlled .................... Figure 40. Deep Power-down Mode .................................... Figure 41. Power-up Mode ................................................ Figure 42. Abnormal Timing .............................................. 112 113 113 114 114 115 115 115
BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . 97
Type 2 pSRAM
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Information . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 98 98 98 99
pSRAM Type 4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Functional Description . . . . . . . . . . . . . . . . . . . . . 116
Product Portfolio ................................................................................................116
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . 117 5
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Operating Range ................................................................................................. 117
Table 35. DC Electrical Characteristics (Over the Operating Range) ..............................................117
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . 118 AC Test Loads and Waveforms . . . . . . . . . . . . . 118
Figure 43. AC Test Loads and Waveforms ............................ 118 Table 36. Switching Characteristics .....................................119
Figure 61. Read Timing #2 (OE# Address Access................. 143 Figure 62. Read Timing #3 (LB#/UB# Byte Access) ............. 144 Figure 63. Read Timing #4 (Page Address Access after CE1# Control Access for 32M and 64M Only) ............................... 144 Figure 64. Read Timing #5 (Random and Page Address Access for 32M and 64M Only) ......................................................... 145
Write Timings .....................................................................................................145
Figure 65. Write Timing #1 (Basic Timing).......................... Figure 66. Write Timing #2 (WE# Control).......................... Figure 67. Write Timing #3-1(WE#/LB#/UB# Byte Write Control) ................................................................. Figure 68. Write Timing #3-3 (WE#/LB#/UB# Byte Write Control) ................................................................. Figure 69. Write Timing #3-4 (WE#/LB#/UB# Byte Write Control) ................................................................. Figure 70. Read/Write Timing #1-1 (CE1# Control) ............. Figure 71. Read / Write Timing #1-2 (CE1#/WE#/OE# Control) ................................................ Figure 72. Read / Write Timing #2 (OE#, WE# Control) ....... Figure 73. Read / Write Timing #3 (OE#, WE#, LB#, UB# Control) ........................................ Figure 74. Power-up Timing #1 ......................................... Figure 75. Power-up Timing #2 ......................................... Figure 76. Power Down Entry and Exit Timing ..................... Figure 77. Standby Entry Timing after Read or Write............ Figure 78. Power Down Program Timing (for 32M/64M Only). 145 146 146 147 147 148 148 149 149 150 150 150 151 151
Switching Waveforms . . . . . . . . . . . . . . . . . . . . 120
Figure 44. Read Cycle 1 (Address Transition Controlled)........ Figure 45. Read Cycle 2 (OE# Controlled) ........................... Figure 46. Write Cycle 1 (WE# Controlled) .......................... Figure 47. Write Cycle 2 (CE#1 or CE2 Controlled) ............... Figure 48. Write Cycle 3 (WE# Controlled, OE# Low)............ Figure 49. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low).. 120 120 121 122 123 123
Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 37. Truth Table ........................................................124
Read/Write Timings ..........................................................................................148
pSRAM Type 6
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Functional Description . . . . . . . . . . . . . . . . . . . . . 126 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 126 AC Characteristics and Operating Conditions . 127 AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . 128 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 129
Read Timings ...................................................................................................... 129
Figure 50. Read Cycle ....................................................... 129 Figure 51. Page Read Cycle (8 Words Access) ...................... 130
SRAM
Common Features . . . . . . . . . . . . . . . . . . . . . . . . 152 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Functional Description . . . . . . . . . . . . . . . . . . . . . 153
4M Version F, 4M version G, 8M version C ......................................... 153 Byte Mode ............................................................................................................ 153
Write Timings ..................................................................................................... 131
Figure 52. Write Cycle #1 (WE# Controlled) (See Note 8) ..... 131 Figure 53. Write Cycle #2 (CE# Controlled) (See Note 8) ...... 132
Deep Power-down Timing ............................................................................. 132
Figure 54. Deep Power Down Timing................................... 132
Functional Description . . . . . . . . . . . . . . . . . . . . . 154
8M Version D .................................................................................................154
Power-on Timing ............................................................................................... 132
Figure 55. Power-on Timing............................................... 132
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 155
Recommended DC Operating Conditions (Note 1) .............................. 155 Capacitance (f=1MHz, TA=25C) .................................................................. 155 DC Operating Characteristics ...................................................................... 155 Common .......................................................................................................... 155 DC Operating Characteristics ......................................................................156 4M Version F ..................................................................................................156 DC Operating Characteristics ......................................................................156 4M Version G .................................................................................................156 DC Operating Characteristics ...................................................................... 157 8M Version C ................................................................................................. 157 DC Operating Characteristics ...................................................................... 157 8M Version D ................................................................................................. 157
Provisions of Address Skew ............................................................................133
Figure 56. Read ............................................................... 133 Figure 57. Write ............................................................... 133
pSRAM Type 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . Power Down (for 32M, 64M Only) . . . . . . . . . . . . 134 134 135 135
Power Down .......................................................................................................135 Power Down Program Sequence ................................................................. 136 Address Key ....................................................................................................... 136
AC Operating Conditions . . . . . . . . . . . . . . . . . . 158
Test Conditions .................................................................................................158
Figure 79. AC Output Load................................................ 158
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 137 Package Capacitance . . . . . . . . . . . . . . . . . . . . . . 137
Power Down Parameters ................................................................................ 141 Other Timing Parameters ............................................................................... 141 AC Test Conditions ......................................................................................... 142 AC Measurement Output Load Circuits ................................................... 142
Figure 58. AC Output Load Circuit - 16 Mb .......................... 142 Figure 59. AC Output Load Circuit - 32 Mb and 64 Mb........... 142
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 158
Read/Write Characteristics (VCC=2.7-3.3V) .............................................158 Data Retention Characteristics (4M Version F) ......................................159 Data Retention Characteristics (4M Version G) .....................................160 Data Retention Characteristics (8M Version C) .....................................160 Data Retention Characteristics (8M Version D) .....................................160 Timing Diagrams ................................................................................................160
Figure 80. Timing Waveform of Read Cycle(1) (Address Controlled, CS#1=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL) ...... 160 Figure 81. Timing Waveform of Read Cycle(2) (WE#=VIH, if BYTE#
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 143
Read Timings ...................................................................................................... 143
Figure 60. Read Timing #1 (Basic Timing) ........................... 143
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is Low, Ignore UB#/LB# Timing) ........................................ 161 Figure 82. Timing Waveform of Write Cycle(1) (WE# controlled, if BYTE# is Low, Ignore UB#/LB# Timing).............................. 161 Figure 83. Timing Waveform of Write Cycle(2) (CS# controlled, if BYTE# is Low, Ignore UB#/LB# Timing).............................. 162 Figure 84. Timing Waveform of Write Cycle(3) (UB#, LB# controlled) ...................................................................... 162 Figure 85. Data Retention Waveform .................................. 163
Write Cycle .........................................................................................................186
Figure 88. Timing Waveform of Read Cycle (WE# = ZZ# = VIH) ................................................ 184 Figure 89. Timing Waveform of Page Mode Read Cycle (WE# = ZZ# = VIH)............................................................................ 185 Figure 90. Timing Waveform of Write Cycle (WE# Control, ZZ# = VIH) ............................................................................... 186 Figure 91. Timing Waveform of Write Cycle (CE# Control, ZZ# = VIH) ............................................................................... 186 Figure 92. Timing Waveform of Page Mode Write Cycle (ZZ# = VIH) 187
pSRAM Type 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . Timing Test Conditions . . . . . . . . . . . . . . . . . . . 164 164 164 170
Output Load Circuit ......................................................................................... 171
Figure 86. Output Load Circuit ........................................... 171
Partial Array Self Refresh (PAR) .................................................................. 188 Temperature Compensated Refresh (for 64Mb) ................................... 188 Deep Sleep Mode ............................................................................................. 188 Reduced Memory Size (for 32M and 16M) ................................................ 188 Other Mode Register Settings (for 64M) ...................................................189
Figure 93. Mode Register .................................................. 189 Figure 94. Mode Register Update Timings (UB#, LB#, OE# are Don't Care)..................................................................... 190 Figure 95. Deep Sleep Mode - Entry/Exit Timings................. 190
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 171 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 183
Read Cycle .......................................................................................................... 183
Figure 87. Timing of Read Cycle (CE# = OE# = VIL, WE# = ZZ# = VIH)................................................................................ 183
Revision Summary
November 22, 2004 S71PL254/127/064/032J_00_A6
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MCP Block Diagram
VCCf
VCC CE#f1 WP#/ACC RESET# Flash-only Address Shared Address OE# WE# VSS RY/BY# Flash 2 (Note 2) Flash 1
CE#f2 (Note 1)
VCCS
DQ15 to DQ0
VCC pSRAM/SRAM
IO15-IO0 CE#s UB#s LB#s CE2 CE# UB# LB#
Notes: 1. For 1 Flash + pSRAM, CE#f1=CE#. For 2 Flash + pSRAM, CE#=CE#f1 and CE#f2 is the chip-enable for the second Flash. 2. For 256Mb only, Flash 1 = Flash 2 = S29PL127J.
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Connection Diagram (S71PL032J)
56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A2 A7 B1 A3 C1 A2 D1 A1 E1 A0 F1 CE1#f G1 CE1#s B2 A6 C2 A5 D2 A4 E2 VSS F2 OE# G2 DQ0 H2 DQ8
A3 LB# B3 UB# C3 A18 D3 A17 E3 DQ1 F3 DQ9 G3 DQ10 H3 DQ2
A4 WP/ACC B4 RST#f C4 RY/BY#
A5 WE# B5 CE2s C5 A20
A6 A8 B6 A19 C6 A9 D6 A10 E6 DQ6
A7 A11 B7 A12 C7 A13 D7 A14 E7 RFU F7 DQ15 G7 DQ7 H7 DQ14 B8 A15 C8 RFU D8 RFU E8 A16 F8 RFU G8 VSS
Legend
Shared (Note 1)
Flash only
RAM only
F4 DQ3 G4 VCCf H4 DQ11
F5 DQ4 G5 VCCs H5 RFU
F6 DQ13 G6 DQ12 H6 DQ5
Reserved for Future Use
Notes: 1. May be shared depending on density.
-- A19 is shared for the 16M pSRAM configuration. -- A18 is shared for the 8M (p)SRAM and above configurations.
2. Connecting all Vcc and Vss balls to Vcc and Vss is recommended.
MCP S71PL032JA0 S71PL032J80 S71PL032J08 S71PL032J40 S71PL032J04
Flash-only Addresses A20 A20-A19 A20-A19 A20-A18 A20-A18
Shared Addresses A19-A0 A18-A0 A18-A0 A17-A0 A17-A0
November 22, 2004 S71PL254/127/064/032J_00_A6
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Connection Diagram (S71PL064J)
56-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A2 A7 B1 A3 C1 A2 D1 A1 E1 A0 F1 CE1#f G1 CE1#s B2 A6 C2 A5 D2 A4 E2 VSS F2 OE# G2 DQ0 H2 DQ8
A3 LB# B3 UB# C3 A18 D3 A17 E3 DQ1 F3 DQ9 G3 DQ10 H3 DQ2
A4 WP/ACC B4 RST#f C4 RY/BY#
A5 WE# B5 CE2s C5 A20
A6 A8 B6 A19 C6 A9 D6 A10 E6 DQ6
A7 A11 B7 A12 C7 A13 D7 A14 E7 RFU F7 DQ15 G7 DQ7 H7 DQ14 B8 A15 C8 A21 D8 RFU E8 A16 F8 RFU G8 VSS
Legend
Shared (Note 1)
Flash only
RAM only
F4 DQ3 G4 VCCf H4 DQ11
F5 DQ4 G5 VCCs H5 RFU
F6 DQ13 G6 DQ12 H6 DQ5
Reserved for Future Use
Notes: 1. May be shared depending on density.
-- A20 is shared for the 32M pSRAM configuration. -- A19 is shared for the 16M pSRAM and above configurations. -- A18 is shared for the 8M (p)SRAM and above configurations.
2. Connecting all Vcc and Vss balls to Vcc and Vss is recommended.
MCP S71PL064JB0 S71PL064JA0 S71PL064J80 S71PL064J08
Flash-only Addresses A21 A21-A20 A21-A19 A21-A19
Shared Addresses A20-A0 A19-A0 A18-A0 A18-A0
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Connection Diagram (S71PL127J)
64-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A1 NC B5 RFU C3 A7 D2 A3 E2 A2 F2 A1 G2 A0 H2 CE#f D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 B6 RFU C6 WE# C7 A8 C8 A11 D8 A12 E8 A13 F8 A14 G8 RFU H8 DQ15 J8 DQ7 K8 DQ14 D9 A15
A10 NC
C4
LB#
C5 WP/ACC D5 RST#f E5 RY/BY#
Legend
D4
UB# E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2
D6
CE2s
D7
A19 E7 A9 F7 A10 G7 DQ6
Shared (Note 1)
E6
A20
E9
A21 F9 A22 G9 A16 H9 RFU J9 VSS
Flash only
RAM only
H5 DQ3 J5 VCCf K5 DQ11 L5 RFU*
H6 DQ4
H7 DQ13 J7 DQ12 K7 DQ5
Reserved for Future Use
J2
CE1#s
J6
VCCs K6 RFU L6 RFU
M1 NC *See notes below
M10 NC
Notes: 1. May be shared depending on density.
-- A21 is shared for the 64M pSRAM configuration. -- A20 is shared for the 32M pSRAM and above configurations.
1. A19 is shared for the 16M pSRAM and above configurations.
MCP S71PL127JC0 S71PL127JB0 S71PL127JA0
Flash-only Addresses A22 A22-A21 A22-A20
Shared Addresses A21-A0 A20-A0 A19-A0
2. Connecting all Vcc & Vss balls to Vcc & Vss is recommended. 3. Ball L5 will be Vccf in the 84-ball density upgrades. Do not connect to Vss or any other signal.
November 22, 2004 S71PL254/127/064/032J_00_A6
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Connection Diagram (S71PL254J)
84-ball Fine-Pitch Ball Grid Array (Top View, Balls Facing Down)
A1 NC B2 RFU C2 RFU D2 A3 E2 A2 F2 A1 G2 A0 H2 CE#f1 B3 RFU C3 A7 D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 L3 RFU B4 RFU B5 CE#F2 C5 WP/ACC D5 RST#f E5 RY/BY# H5 RFU H5 RFU H5 DQ3 J5 VCCf K5 DQ11 L5 VCCf B6 RFU C6 WE# B7 RFU C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 L7 RFU B8 RFU C8 A11 D8 A12 E8 A13 F8 A14 G8 RFU H8 DQ15 J8 DQ7 K8 DQ14 L8 RFU B9 RFU C9 RFU D9 A15
A10 NC
C4
LB#
Legend
D4
UB# E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 L4 RFU
D6
CE2s
Shared (Note 1)
E6
A20 H6 RFU H6 RFU H6 DQ4
E9
A21 F9 A22 G9 A16 H9 RFU J9 VSS K9 RFU L9 RFU M10 NC 2nd Flash Only
Flash only
RAM only
Reserved for Future Use
J2
CE1#s K2 RFU L2 RFU M1 NC
J6
VCCs K6 RFU L6 RFU
Notes: 1. May be shared depending on density.
-- A21 is shared for the 64M pSRAM configuration. -- A20 is shared for the 32M pSRAM configuration.
MCP S71PL254JC0 S71PL254JB0
Flash-only Addresses A22 A22-A21
Shared Addresses A21-A0 A20-A0
2. Connecting all Vcc & Vss balls to Vcc & Vss is recommended.
Special Handling Instructions For FBGA Package
Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised
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if the package body is exposed to temperatures above 150C for prolonged periods of time.
Pin Description
A21-A0 DQ15-DQ0 CE1#f CE#f2 CE1#ps CE2ps OE# WE# RY/BY# UB# LB# RESET# WP#/ACC VCCf = = = = = = = = = = = = = = 22 Address Inputs (Common) 16 Data Inputs/Outputs (Common) Chip Enable 1 (Flash) Chip Enable 2 (Flash) Chip Enable 1 (pSRAM) Chip Enable 2 (pSRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output (Flash 1) Upper Byte Control (pSRAM) Lower Byte Control (pSRAM) Hardware Reset Pin, Active Low (Flash 1) Hardware Write Protect/Acceleration Pin (Flash) Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) pSRAM Power Supply Device Ground (Common) Pin Not Connected Internally
VCCps VSS NC
= = =
Logic Symbol
22 A21-A0
16 CE1#f CE2#f CE1#ps CE2ps OE# WE# WP#/ACC RESET# UB# LB# RY/BY# DQ15-DQ0
November 22, 2004 S71PL254/127/064/032J_00_A6
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Ordering Information
The order number is formed by a valid combinations of the following: S71PL 127 J B0 BA W 9 Z 0
PACKING TYPE 0 = Tray 2 = 7" Tape and Reel 3 = 13" Tape and Reel MODEL NUMBER See the Valid Combinations table. PACKAGE MODIFIER 0 = 7 x 9mm, 1.2mm height, 56 balls (TLC056 or TSC065) 9 = 8 x 11.6mm, 1.2mm height, 64 balls (TLA064 or TSB064) T = 8 x 11.6mm, 1.4mm height, 84 balls (FTA084) TEMPERATURE RANGE W = Wireless (-25C to +85C) I = Industrial (-40C to +85C) PACKAGE TYPE BA = Fine-pitch BGA Lead (Pb)-free compliant package BF = Fine-pitch BGA Lead (Pb)-free package pSRAM C0 = B0 = A0 = 80 = 40 = 08 = 04 = DENSITY 64Mb pSRAM 32Mb pSRAM 16Mb pSRAM 8Mb pSRAM 4Mb pSRAM 8Mb SRAM 4Mb SRAM
PROCESS TECHNOLOGY J = 110 nm, Floating Gate Technology FLASH DENSITY 254 = 256Mb 127 = 128Mb 064 = 64Mb 032 = 32Mb PRODUCT FAMILY S71PL Multi-chip Product (MCP) 3.0-volt Simultaneous Read/Write, Page Mode Flash Memory and RAM
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S71PL254/127/064/032J_00_A6 November 22, 2004
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S71PL032J Valid Combinations Base Ordering Part Number S71PL032J04 S71PL032J04 S71PL032J04 S71PL032J40 S71PL032J80 S71PL032J08 S71PL032J40 S71PL032J80 S71PL032JA0 S71PL032JA0 S71PL032JA0 S71PL032J04 S71PL032J04 S71PL032J04 S71PL032J40 S71PL032J80 S71PL032J08 S71PL032J40 S71PL032J80 S71PL032JA0 S71PL032JA0 S71PL032JA0 S71PL032J04 S71PL032J04 S71PL032J04 S71PL032J40 S71PL032J80 S71PL032J08 S71PL032J40 S71PL032J80 S71PL032JA0 S71PL032JA0 S71PL032JA0 S71PL032J04 S71PL032J04 S71PL032J04 S71PL032J40 S71PL032J80 S71PL032J08 S71PL032J40 S71PL032J80 S71PL032JA0 S71PL032JA0 S71PL032JA0 BFI BAI BFW BAW Package & Temperature Package Modifier/ Model Number 0B 0F 0K 0K 0P 0B 07 07 07 0F 0Z 0B 0F 0K 0K 0P 0B 07 07 07 0F 0Z 0B 0F 0K 0K 0P 0B 07 07 07 0F 0Z 0B 0F 0K 0K 0P 0B 07 07 07 0F 0Z 65 0, 2, 3 (Note 1) 65 65 0, 2, 3 (Note 1) 65 65 0, 2, 3 (Note 1) 65 65 0, 2, 3 (Note 1) 65 Packing Type Speed Options (ns)
(p)SRAM Type/Access Time (ns) SRAM2 / 70 SRAM3 / 70 SRAM4 / 70 pSRAM4 / 70 pSRAM5 / 70 SRAM2 / 70 pSRAM1 / 70 pSRAM1 / 70 pSRAM1 / 70 pSRAM3 / 70 pSRAM2 / 70 SRAM2 / 70 SRAM3 / 70 SRAM4 / 70 pSRAM4 / 70 pSRAM5 / 70 SRAM2 / 70 pSRAM1 / 70 pSRAM1 / 70 pSRAM1 / 70 pSRAM3 / 70 pSRAM2 / 70 SRAM2 / 70 SRAM3 / 70 SRAM4 / 70 pSRAM4 / 70 pSRAM5 / 70 SRAM2 / 70 pSRAM1 / 70 pSRAM1 / 70 pSRAM1 / 70 pSRAM3 / 70 pSRAM2 / 70 SRAM2 / 70 SRAM3 / 70 SRAM4 / 70 pSRAM4 / 70 pSRAM5 / 70 SRAM2 / 70 pSRAM1 / 70 pSRAM1 / 70 pSRAM1 / 70 pSRAM3 / 70 pSRAM2 / 70
Package Marking
(Note 2)
(Note 2)
(Note 2)
(Note 2)
November 22, 2004 S71PL254/127/064/032J_00_A6
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Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S" and packing type designator from ordering part number.
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
S71PL064J Valid Combinations Base Ordering Part Number S71PL064J08 S71PL064J08 S71PL064J80 S71PL064J80 S71PL064J80 S71PL064JA0 S71PL064JA0 S71PL064JA0 S71PL064JA0 S71PL064JB0 S71PL064JB0 S71PL064JB0 S71PL064J08 S71PL064J08 S71PL064J80 S71PL064J80 S71PL064J80 S71PL064JA0 S71PL064JA0 S71PL064JA0 S71PL064JA0 S71PL064JB0 S71PL064JB0 S71PL064JB0 S71PL064J08 S71PL064J08 S71PL064J80 S71PL064J80 S71PL064J80 S71PL064JA0 S71PL064JA0 S71PL064JA0 S71PL064JA0 S71PL064JB0 S71PL064JB0 S71PL064JB0 BAI BFW BAW Package & Temperature Package Modifier/ Model Number 0B 0U 0K 07 0P 0Z 0B 07 0P 07 0B 0U 0B 0U 0K 07 0P 0Z 0B 07 0P 07 0B 0U 0B 0U 0K 07 0P 0Z 0B 07 0P 07 0B 0U 0, 2, 3 (Note 1) 65 0, 2, 3 (Note 1) 65 0, 2, 3 (Note 1) 65 Packing Type Speed Options (ns)
(p)SRAM Type/Access Time (ns) SRAM1 / 70 SRAM3 / 70 pSRAM1 /70 pSRAM1 / 70 pSRAM5 / 70 pSRAM7 / 70 pSRAM3 / 70 pSRAM1 / 70 pSRAM7 / 70 pSRAM1 / 70 pSRAM2 / 70 pSRAM6 / 70 SRAM1 / 70 SRAM3 / 70 pSRAM1 /70 pSRAM1 / 70 pSRAM5 / 70 pSRAM7 / 70 pSRAM3 / 70 pSRAM1 / 70 pSRAM7 / 70 pSRAM1 / 70 pSRAM2 / 70 pSRAM6 / 70 SRAM1 / 70 SRAM3 / 70 pSRAM1 /70 pSRAM1 / 70 pSRAM5 / 70 pSRAM7 / 70 pSRAM3 / 70 pSRAM1 / 70 pSRAM7 / 70 pSRAM1 / 70 pSRAM2 / 70 pSRAM6 / 70
Package Marking
(Note 2)
(Note 2)
(Note 2)
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S71PL254/127/064/032J_00_A6 November 22, 2004
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S71PL064J Valid Combinations Base Ordering Part Number S71PL064J08 S71PL064J08 S71PL064J80 S71PL064J80 S71PL064J80 S71PL064JA0 S71PL064JA0 S71PL064JA0 S71PL064JA0 S71PL064JB0 S71PL064JB0 S71PL064JB0 BFI Package & Temperature Package Modifier/ Model Number 0B 0U 0K 07 0P 0Z 0B 07 0P 07 0B 0U 0, 2, 3 (Note 1) 65 Packing Type Speed Options (ns)
(p)SRAM Type/Access Time (ns) SRAM1 / 70 SRAM3 / 70 pSRAM1 /70 pSRAM1 / 70 pSRAM5 / 70 pSRAM7 / 70 pSRAM3 / 70 pSRAM1 / 70 pSRAM7 / 70 pSRAM1 / 70 pSRAM2 / 70 pSRAM6 / 70
Package Marking
(Note 2)
Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S" and packing type designator from ordering part number.
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
S71PL127J Valid Combinations Base Ordering Part Number S71PL127JA0 S71PL127JA0 S71PL127JA0 S71PL127JB0 S71PL127JB0 S71PL127JB0 S71PL127JC0 S71PL127JC0 S71PL127JC0 S71PL127JB0 S71PL127JA0 S71PL127JA0 S71PL127JA0 S71PL127JB0 S71PL127JB0 S71PL127JB0 S71PL127JC0 S71PL127JC0 S71PL127JC0 S71PL127JB0 BFW BAW Package & Temperature Package Modifier/Model Number 9P 9Z 97 97 9Z 9U 97 9Z 9U 9B 9P 9Z 97 97 9Z 9U 97 9Z 9U 9B 0, 2, 3 (Note 1) 65 0, 2, 3 (Note 1) 65
Packing Type
Speed Options (ns)
(p)SRAM Type/Access Time (ns) pSRAM7 / 70 pSRAM7 / 70 pSRAM1 / 70 pSRAM1 / 70 pSRAM7 / 70 pSRAM6 /70 pSRAM1 /70 pSRAM7 / 70 pSRAM6 / 70 pSRAM2 / 70 pSRAM7 / 70 pSRAM7 / 70 pSRAM1 / 70 pSRAM1 / 70 pSRAM7 / 70 pSRAM6 / 70 pSRAM1 /70 pSRAM7 / 70 pSRAM6 / 70 pSRAM2 / 70
Package Marking
(Note 2)
(Note 2)
November 22, 2004 S71PL254/127/064/032J_00_A6
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S71PL127J Valid Combinations Base Ordering Part Number S71PL127JA0 S71PL127JA0 S71PL127JA0 S71PL127JB0 S71PL127JB0 S71PL127JB0 S71PL127JC0 S71PL127JC0 S71PL127JC0 S71PL127JB0 S71PL127JA0 S71PL127JA0 S71PL127JA0 S71PL127JB0 S71PL127JB0 S71PL127JB0 S71PL127JB0 S71PL127JC0 S71PL127JC0 S71PL127JC0 BFI BAI Package & Temperature Package Modifier/Model Number 9P 9Z 97 97 9Z 9U 97 9Z 9U 9B 9P 9Z 97 97 9Z 9U 9B 97 9Z 9U 0, 2, 3 (Note 1) 65 0, 2, 3 (Note 1) 65
Packing Type
Speed Options (ns)
(p)SRAM Type/Access Time (ns) pSRAM7 / 70 pSRAM7 / 70 pSRAM1 / 70 pSRAM1 / 70 pSRAM7 / 70 pSRAM6 / 70 pSRAM1 /70 pSRAM7 / 70 pSRAM6 / 70 pSRAM2 / 70 pSRAM7 / 70 pSRAM7 / 70 pSRAM1 / 70 pSRAM1 / 70 pSRAM7 / 70 pSRAM6 / 70 pSRAM2 / 70 pSRAM1 /70 pSRAM7 / 70 pSRAM6 / 70
Package Marking
(Note 2)
(Note 2)
Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S" and packing type designator from ordering part number.
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
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S71PL254J Valid Combinations Base Ordering Part Number S71PL254JB0 S71PL254JB0 S71PL254JB0 S71PL254JC0 S71PL254JC0 S71PL254JB0 S71PL254JB0 S71PL254JB0 S71PL254JC0 S71PL254JC0 S71PL254JB0 S71PL254JB0 S71PL254JB0 S71PL254JC0 S71PL254JC0 S71PL254JB0 S71PL254JB0 S71PL254JB0 S71PL254JC0 S71PL254JC0 BFI BAI BFW BAW Package & Temperature Model Number T7 TB TU TB TZ T7 TB TU TB TZ T7 TB TU TB TZ T7 TB TU TB TZ 0, 2, 3 (Note 1) 65 0, 2, 3 (Note 1) 65 0, 2, 3 (Note 1) 65 0, 2, 3 (Note 1) 65 Packing Type Speed Options (ns)
(p)SRAM Type/Access Time (ns) pSRAM1 / 70 pSRAM2 /70 pSRAM6 / 70 pSRAM2 / 70 pSRAM7 / 70 pSRAM1 / 70 pSRAM2 /70 pSRAM6 / 70 pSRAM2 / 70 pSRAM7 / 70 pSRAM1 / 70 pSRAM2 /70 pSRAM6 / 70 pSRAM2 / 70 pSRAM7 / 70 pSRAM1 / 70 pSRAM2 /70 pSRAM6 / 70 pSRAM2 / 70 pSRAM7 / 70
Package Marking
(Note 2)
(Note 2)
(Note 2)
(Note 2)
Notes: 1. Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading "S" and packing type designator from ordering part number.
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.
November 22, 2004 S71PL254/127/064/032J_00_A6
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Physical Dimensions
TLC056--56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7mm Package
D
0.15 C (2X)
8 7 6
A
D1 eD
SE 7 E1
E eE
5 4 3 2 1
INDEX MARK PIN A1 CORNER 10
H
G
F
E
D
CB
A
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW
0.20 C
A A2 A1
6
C
0.08 C
SIDE VIEW b
56X
0.15 M C A B 0.08 M C
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.35 TLC 056 N/A 9.00 mm x 7.00 mm PACKAGE MIN --0.20 0.81 NOM ------9.00 BSC. 7.00 BSC. 5.60 BSC. 5.60 BSC. 8 8 56 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. A1,A8,D4,D5,E4,E5,H1,H8 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3348 \ 16-038.22a
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TSC056--56-ball Fine-Pitch Ball Grid Array (FBGA) 9 x 7mm Package
D
0.15 C (2X)
8 7 6
A
D1 eD
SE
7
E eE
5 4 3 2 1
E1
INDEX MARK PIN A1 CORNER 10
H
G
F
E
D
CB
A
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW A A2 A1
6
0.20 C
C
0.08 C
SIDE VIEW b
MCAB MC
56X
0.15 0.08
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.35 TSC 056 N/A 9.00 mm x 7.00 mm PACKAGE MIN --0.17 0.81 NOM ------9.00 BSC. 7.00 BSC. 5.60 BSC. 5.60 BSC. 8 8 56 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. A1,A8,D4,D5,E4,E5,H1,H8 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3427 \ 16-038.22
November 22, 2004 S71PL254/127/064/032J_00_A6
21
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Information
TLA064--64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6mm Package
D
0.15 C (2X)
10 9 8 7
A
D1 eD
SE
7
E eE
6 5 4 3 2 1 L J H G F E D CB A
E1
INDEX MARK PIN A1 CORNER 10
M
K
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW A A2 A1
64X
0.15 0.08
0.20 C
6
SIDE VIEW b
M C AB MC
C
0.08 C
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.35 TLA 064 N/A 11.60 mm x 8.00 mm PACKAGE MIN --0.17 0.81 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 64 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B2,B3,B4,B7,B8,B9,B10 C1,C2,C9,C10,D1,D10,E1,E10, F1,F5,F6,F10,G1,G5,G6,G10 H1,H10,J1,J10,K1,K2,K9,K10 L1,L2,L3,L4,L7,L8,L9,L10 M2,M3,M4,M5,M6,M7,M8,M9
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3352 \ 16-038.22a
22
S71PL254/127/064/032J_00_A6 November 22, 2004
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TSB064--64-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6 mm Package
D
0.15 C (2X)
10 9 8 7
A
D1 eD
SE
7
E eE
6 5 4 3 2 1 L J H G F E D CB A
E1
INDEX MARK PIN A1 CORNER 10
M
K
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW A A2 A1
64X
0.15 0.08
0.20 C
6
SIDE VIEW b
M C AB MC
C
0.08 C
PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.35
TSB 064 N/A 11.60 mm x 8.00 mm PACKAGE MIN --017 0.81 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 64 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT NOTE
NOTES: 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 7 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B2,B3,B4,B7,B8,B9,B10 C1,C2,C9,C10,D1,D10,E1,E10 F1,F5,F6,F10,G1,G5,G6,G10 H1,H10,J1,J10,K1,K2,K9,K10 L1,L2,L3,L4,L7,L8,L9,L10 M2,M3,M4,M5,M6,M7,M8,M9
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3351 \ 16-038.22a
November 22, 2004 S71PL254/127/064/032J_00_A6
23
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Information
FTA084--84-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 11.6mm
D
0.15 C (2X)
10 9 8 7 6 5 4
A
D1 eD
SE
7
E eE
INDEX MARK PIN A1 CORNER 10
E1
3 2 1 MLKJ HG F EDC BA
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW
0.20 C
A A2 A1
6
C
0.08 C
SIDE VIEW b
84X
0.15 M C A B 0.08 M C
NOTES: PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.35 FTA 084 N/A 11.60 mm x 8.00 mm PACKAGE MIN --0.17 1.02 NOM ------11.60 BSC. 8.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 84 0.40 0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.40 --1.17 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT 9. 8. 7 6 NOTE 2. 3. 4. 5. 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B10,C1,C10,D1,D10,E1,E10 F1,F10,G1,G10,H1,H10 J1,J10,K1,K10,L1,L10 M2,M3,M4,M5,M6,M7,M8,M9
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3388 \ 16-038.21a
24
S71PL254/127/064/032J_00_A6 November 22, 2004
S29PL127J/S29PL064J/S29PL032J for MCP
128/64/32 Megabit (8/4/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory with Enhanced VersatileIOTM Control
ADVANCE INFORMATION
Distinctive Characteristics
Architectural Advantages
128/64/32 Mbit Page Mode devices -- Page size of 8 words: Fast page read access from random locations within the page Single power supply operation -- Full Voltage range: 2.7 to 3.1 volt read, erase, and program operations for battery-powered applications Simultaneous Read/Write Operation -- Data can be continuously read from one bank while executing erase/program functions in another bank -- Zero latency switching from write to read operations FlexBank Architecture (PL127J/PL064J/PL032J) -- 4 separate banks, with up to two simultaneous operations per device -- Bank A: PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31) PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15) PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7) -- Bank B: PL127J - 48 Mbit (32 Kw x 96) PL064J - 24 Mbit (32 Kw x 48) PL032J - 12 Mbit (32 Kw x 24) -- Bank C: PL127J - 48 Mbit (32 Kw x 96) PL064J - 24 Mbit (32 Kw x 48) PL032J - 12 Mbit (32 Kw x 24) -- Bank D: PL127J -16 Mbit (4 Kw x 8 and 32 Kw x 31) PL064J - 8 Mbit (4 Kw x 8 and 32 Kw x 15) PL032J - 4 Mbit (4 Kw x 8 and 32 Kw x 7) Enhanced VersatileI/OTM (VIO) Control -- Output voltage generated and input voltages tolerated on all control inputs and I/Os is determined by the voltage on the VIO pin -- VIO options at 1.8 V and 3 V I/O for PL127J devices -- 3V VIO for PL064J and PL032J devices Secured Silicon Sector region -- Up to 128 words accessible through a command sequence -- Up to 64 factory-locked words -- Up to 64 customer-lockable words Both top and bottom boot blocks in one device Manufactured on 110 nm process technology Data Retention: 20 years typical Cycling Endurance: 1 million cycles per sector typical
Performance CharacteristicS
High Performance -- Page access times as fast as 20 ns -- Random access times as fast as 55 ns Power consumption (typical values at 10 MHz) -- 45 mA active read current -- 17 mA program/erase current -- 0.2 A typical standby mode current
Software Features
Software command-set compatible with JEDEC 42.4 standard -- Backward compatible with Am29F, Am29LV, Am29DL, and AM29PDL families and MBM29QM/RM, MBM29LV, MBM29DL, MBM29PDL families CFI (Common Flash Interface) compliant -- Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices Erase Suspend / Erase Resume -- Suspends an erase operation to allow read or program operations in other sectors of same bank Unlock Bypass Program command -- Reduces overall programming time when issuing multiple program command sequences
Publication Number S29PL127J_064J_032J_MCP
Revision A
Amendment 3
Issue Date August 12, 2004
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Information
Hardware Features
Ready/Busy# pin (RY/BY#) -- Provides a hardware method of detecting program or erase cycle completion Hardware reset pin (RESET#) -- Hardware method to reset the device to reading array data WP#/ ACC (Write Protect/Acceleration) input -- At VIL, hardware level protection for the first and last two 4K word sectors. -- At VIH, allows removal of sector protection -- At VHH, provides accelerated programming in a factory setting Persistent Sector Protection -- A command sector protection method to lock combinations of individual sectors and sector groups
to prevent program or erase operations within that sector -- Sectors can be locked and unlocked in-system at VCC level Password Sector Protection -- A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password Package options -- Standard discrete pinouts 11 x 8 mm, 80-ball Fine-pitch BGA (PL127J) (VBG080) 8 x 6 mm, 48-ball Fine pitch BGA (PL064J/PL032J) (VBK048) -- MCP-compatible pinout 8 x 11.6 mm, 64-ball Fine-pitch BGA (PL127J) 7 x 9 mm, 56-ball Fine-pitch BGA (PL064J and PL032J) Compatible with MCP pinout, allowing easy integration of RAM into existing designs
26
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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General Description
The PL127J/PL064J/PL032J is a 128/128/64/32 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory device organized as 8/8/4/2 Mwords. The devices are offered in the following packages: 11mm x 8mm, 64-ball Fine-pitch BGA standalone (all) 9mm x 8mm, 80-ball Fine-pitch BGA standalone (PL127J) 8mm x 11.6mm, 64-ball Fine pitch BGA multi-chip compatible (PL127J) The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations. The device offers fast page access times of 20 to 30 ns, with corresponding random access times of 55 to 70 ns, respectively, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.
Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). This releases the system from waiting for the completion of a program or erase operation, greatly improving system performance. The device can be organized in both top and bottom sector configurations. The banks are organized as follows: Bank A B C D PL127J Sectors 16 Mbit (4 Kw x 8 and 32 Kw x 31) 48 Mbit (32 Kw x 96) 48 Mbit (32 Kw x 96) 16 Mbit (4 Kw x 8 and 32 Kw x 31) PL064J Sectors 8 Mbit (4 Kw x 8 and 32 Kw x 15) 24 Mbit (32 Kw x 48) 24 Mbit (32 Kw x 48) 8 Mbit (4 Kw x 8 and 32 Kw x 15) PL032J Sectors 4 Mbit (4 Kw x 8 and 32 Kw x 7) 12 Mbit (32 Kw x 24) 12 Mbit (32 Kw x 24) 4 Mbit (4 Kw x 8 and 32 Kw x 7)
Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page mode operation provides fast read access speed of random locations within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC 42.4 singlepower-supply Flash standard. Commands are written to the command register using standard microprocessor write timing. Register contents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
27
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Information
and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. If a read is needed from the Secured Silicon Sector area (One Time Program area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. The device electrically erases all bits within a sector simultaneously via FowlerNordheim tunneling. The data is programmed using hot electron injection.
28
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Product Selector Guide
Part Number VCC,VIO = 2.7-3.6 V Speed Option VCC = 2.7-3.6 V, VIO = 1.65-1.95 V (PL127J only) 55 (Note) 60 55 (Note) S29PL032J/S29PL064J/S29PL127J 60 65 65 70 70 70 70
Max Access Time, ns (tACC) Max CE# Access, ns (tCE) Max Page Access, ns (tPACC) Max OE# Access, ns (tOE) Note: Contact factory for availability.
20 (Note)
25
30
30
30
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
29
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Information
Block Diagram
DQ15-DQ0
RY/BY# (See Note)
VCC VSS
Sector Switches
VIO
RESET#
Input/Output Buffers
Erase Voltage Generator
WE#
State Control Command Register
PGM Voltage Generator
CE# OE#
Chip Enable Output Enable Logic
Data Latch
Y-Decoder
Y-Gating
VCC Detector
Timer
Address Latch
Amax-A3
X-Decoder
Cell Matrix
A2-A0
Notes: 1. RY/BY# is an open drain output. 2. Amax = A22 (PL127J), A21 (PL064J), A20 (PL032J)
30
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Information
Simultaneous Read/Write Block Diagram
VCC VSS
OE#
Mux
Bank A
Bank A Address
Amax-A0
Y-gate
X-Decoder
A22-A0
RY/BY#
Bank B Address
Bank B X-Decoder
DQ15-DQ0
Amax-A0
RESET# WE# CE# WP#/ACC
STATE CONTROL & COMMAND REGISTER
Status
DQ15-DQ0
DQ15-DQ0
Control
DQ15-DQ0
Mux
DQ0-DQ15
A22-A0
Bank C Address
X-Decoder Bank C
Y-gate
X-Decoder
Amax-A0
Mux
Bank D Address
Bank D
Note: Amax = A22 (PL127J), A21 (PL064J), A20 (PL032J) Note: Pinout shown for PL127J.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
DQ15-DQ0
31
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Information
Pin Description
Amax-A0 DQ15-DQ0 CE# OE# WE# VSS NC RY/BY# = = = = = = = = Address bus 16-bit data inputs/outputs/float Chip Enable Inputs Output Enable Input Write Enable Device Ground Pin Not Connected Internally Ready/Busy output and open drain. When RY/BY#= VIH, the device is ready to accept read operations and commands. When RY/BY#= VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset operation. Write Protect/Acceleration Input. When WP#/ACC= VIL, the highest and lowest two 4K-word sectors are write protected regardless of other sector protection configurations. When WP#/ ACC= VIH, these sector are unprotected unless the DYB or PPB is programmed. When WP#/ACC= 12V, program and erase operations are accelerated. Input/Output Buffer Power Supply (1.65 V to 1.95 V (for PL127J) or 2.7 V to 3.6 V (for all PLxxxJ devices) Chip Power Supply (2.7 V to 3.6 V or 2.7 to 3.3 V) Hardware Reset Pin Chip Enable Inputs
WP#/ACC
=
VIO VCC RESET# CE#1
=
= = =
Notes: 1. Amax = A22 (PL127J), A21 (PL064J), A20 (PL032J)
Logic Symbol
max+1 Amax-A0 DQ15-DQ0 CE# OE# WE# WP#/ACC RESET# RY/BY# 16
VIO (VCCQ)
32
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Information
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Table 1.
Operation Read Write Standby Output Disable Reset Temporary Sector Unprotect (High Voltage)
PL127J Device Bus Operations
OE# L H X H X X WE# H L X H X X RESET# H H VIO 0.3 V H L VID WP#/ACC X X (Note 2) X (Note 2) X X X Addresses (Amax-A0) AIN AIN X X X AIN DQ15- DQ0 DOUT DIN High-Z High-Z High-Z DIN
CE# L L VIO 0.3 V L X X
Legend: L= Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 8.5-9.5 V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes: 1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the High Voltage Sector Protection section. 2. WP#/ACC must be high when writing to upper two and lower two sectors.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the OE# and appropriate CE# pins. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to Table 23 for timing specifications and to Figure 11 for the timing diagram. ICC1 in the DC Characteristics table represents the active current specification for reading array data.
Random Read (Non-Page Read)
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from the stable addresses and stable CE# to valid data at the output inputs. The output enable
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
33
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Information
access time is the delay from the falling edge of the OE# to valid data at the output inputs (assuming the addresses have been stable for at least tACC-tOE time).
Page Mode Read
The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. Address bits Amax-A3 select an 8 word page, and address bits A2-A0 select a specific word within that page. This is an asynchronous operation with the microprocessor supplying the specific word location. The random or initial page access is tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. Fast page mode accesses are obtained by keeping Amax-A3 constant and changing A2-A0 to select the specific word within that page.
Table 2.
Word Word 0 Word 1 Word 2 Word 3 Word 4 Word 5 Word 6 Word 7
Page Select
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1
Simultaneous Read/Write Operation
In addition to the conventional features (read, program, erase-suspend read, and erase-suspend program), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation). The bank can be selected by bank addresses (PL127J: A22-A20, L064J: A21-A19, PL032J: A20-A18) with zero latency. The simultaneous operation can execute multi-function mode in the same bank.
Table 3.
Bank Select PL127J: A22-A20 PL064J: A21-A19 PL032J: A20-A18
000 001, 010, 011 100, 101, 110 111
Bank Bank A Bank B Bank C Bank D
34
S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Information
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required to program a word, instead of four. The "Word Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 4 indicates the set of address space that each sector occupies. A "bank address" is the set of address bits required to uniquely select a bank. Similarly, a "sector address" refers to the address bits required to uniquely select a sector. The "Command Definitions" section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. ICC2 in the DC Characteristics table represents the active current specification for the write mode. See the timing specification tables and timing diagrams in the Reset for write operations.
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This function is primarily intended to allow faster manufacturing throughput at the factory. If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin should be raised to VCC when not in use. That is, the WP#/ACC pin should not be left floating or unconnected; inconsistent behavior of the device may result.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ15-DQ0. Standard read cycle timings apply in this mode. Refer to the Secured Silicon Sector Addresses and Autoselect Command Sequence for more information.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO 0.3 V. (Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VIO 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
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requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC3 in "DC Characteristics" represents the CMOS standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Note that during automatic sleep mode, OE# must be at VIH before the device reduces current to the stated sleep mode specification. ICC5 in "DC Characteristics" represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a "0" (busy) until the internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/ BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is "1"), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH. Refer to the AC Characteristic tables for RESET# parameters and to 13 for the timing diagOutput Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins (except for RY/BY#) are placed in the highest Impedance state.
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Table 4.
Bank Sector
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 Bank A SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
PL127J Sector Architecture
Sector Size (Kwords)
4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Sector Address (A22-A12)
00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000010XXX 00000011XXX 00000100XXX 00000101XXX 00000110XXX 00000111XXX 00001000XXX 00001001XXX 00001010XXX 00001011XXX 00001100XXX 00001101XXX 00001110XXX 00001111XXX 00010000XXX 00010001XXX 00010010XXX 00010011XXX 00010100XXX 00010101XXX 00010110XXX 00010111XXX 00011000XXX 00011001XXX 00011010XXX 00011011XXX 00011100XXX 00011101XXX 00011110XXX 00011111XXX
Address Range (x16)
000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh
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Table 4.
Bank Sector
SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 Bank B SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78
PL127J Sector Architecture (Continued)
Sector Address (A22-A12)
00100000XXX 00100001XXX 00100010XXX 00100011XXX 00100100XXX 00100101XXX 00100110XXX 00100111XXX 00101000XXX 00101001XXX 00101010XXX 00101011XXX 00101100XXX 00101101XXX 00101110XXX 00101111XXX 00110000XXX 00110001XXX 00110010XXX 00110011XXX 00110100XXX 00110101XXX 00110110XXX 00110111XXX 00111000XXX 00111001XXX 00111010XXX 00111011XXX 00111100XXX 00111101XXX 00111110XXX 00111111XXX 01000000XXX 01000001XXX 01000010XXX 01000011XXX 01000100XXX 01000101XXX 01000110XXX 01000111XXX
Sector Size (Kwords)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Address Range (x16)
100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh
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S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Table 4.
Bank Sector
SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 Bank B SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118
PL127J Sector Architecture (Continued)
Sector Address (A22-A12)
01001000XXX 01001001XXX 01001010XXX 01001011XXX 01001100XXX 01001101XXX 01001110XXX 01001111XXX 01010000XXX 01010001XXX 01010010XXX 01010011XXX 01010100XXX 01010101XXX 01010110XXX 01010111XXX 01011000XXX 01011001XXX 01011010XXX 01011011XXX 01011100XXX 01011101XXX 01011110XXX 01011111XXX 01100000XXX 01100001XXX 01100010XXX 01100011XXX 01100100XXX 01100101XXX 01100110XXX 01100111XXX 01101000XXX 01101001XXX 01101010XXX 01101011XXX 01101100XXX 01101101XXX 01101110XXX 01101111XXX
Sector Size (Kwords)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Address Range (x16)
240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh
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Table 4.
Bank Sector
SA119 SA120 SA121 SA122 SA123 SA124 SA125 Bank B SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 Bank C SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158
PL127J Sector Architecture (Continued)
Sector Address (A22-A12)
01110000XXX 01110001XXX 01110010XXX 01110011XXX 01110100XXX 01110101XXX 01110110XXX 01110111XXX 01111000XXX 01111001XXX 01111010XXX 01111011XXX 01111100XXX 01111101XXX 01111110XXX 01111111XXX 10000000XXX 10000001XXX 10000010XXX 10000011XXX 10000100XXX 10000101XXX 10000110XXX 10000111XXX 10001000XXX 10001001XXX 10001010XXX 10001011XXX 10001100XXX 10001101XXX 10001110XXX 10001111XXX 10010000XXX 10010001XXX 10010010XXX 10010011XXX 10010100XXX 10010101XXX 10010110XXX 10010111XXX
Sector Size (Kwords)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Address Range (x16)
380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh 400000h-407FFFh 408000h-40FFFFh 410000h-417FFFh 418000h-41FFFFh 420000h-427FFFh 428000h-42FFFFh 430000h-437FFFh 438000h-43FFFFh 440000h-447FFFh 448000h-44FFFFh 450000h-457FFFh 458000h-45FFFFh 460000h-467FFFh 468000h-46FFFFh 470000h-477FFFh 478000h-47FFFFh 480000h-487FFFh 488000h-48FFFFh 490000h-497FFFh 498000h-49FFFFh 4A0000h-4A7FFFh 4A8000h-4AFFFFh 4B0000h-4B7FFFh 4B8000h-4BFFFFh
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Table 4.
Bank Sector
SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 Bank C SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198
PL127J Sector Architecture (Continued)
Sector Address (A22-A12)
10011000XXX 10011001XXX 10011010XXX 10011011XXX 10011100XXX 10011101XXX 10011110XXX 10011111XXX 10100000XXX 10100001XXX 10100010XXX 10100011XXX 10100100XXX 10100101XXX 10100110XXX 10100111XXX 10101000XXX 10101001XXX 10101010XXX 10101011XXX 10101100XXX 10101101XXX 10101110XXX 10101111XXX 10110000XXX 10110001XXX 10110010XXX 10110011XXX 10110100XXX 10110101XXX 10110110XXX 10110111XXX 10111000XXX 10111001XXX 10111010XXX 10111011XXX 10111100XXX 10111101XXX 10111110XXX 10111111XXX
Sector Size (Kwords)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Address Range (x16)
4C0000h-4C7FFFh 4C8000h-4CFFFFh 4D0000h-4D7FFFh 4D8000h-4DFFFFh 4E0000h-4E7FFFh 4E8000h-4EFFFFh 4F0000h-4F7FFFh 4F8000h-4FFFFFh 500000h-507FFFh 508000h-50FFFFh 510000h-517FFFh 518000h-51FFFFh 520000h-527FFFh 528000h-52FFFFh 530000h-537FFFh 538000h-53FFFFh 540000h-547FFFh 548000h-54FFFFh 550000h-557FFFh 558000h-15FFFFh 560000h-567FFFh 568000h-56FFFFh 570000h-577FFFh 578000h-57FFFFh 580000h-587FFFh 588000h-58FFFFh 590000h-597FFFh 598000h-59FFFFh 5A0000h-5A7FFFh 5A8000h-5AFFFFh 5B0000h-5B7FFFh 5B8000h-5BFFFFh 5C0000h-5C7FFFh 5C8000h-5CFFFFh 5D0000h-5D7FFFh 5D8000h-5DFFFFh 5E0000h-5E7FFFh 5E8000h-5EFFFFh 5F0000h-5F7FFFh 5F8000h-5FFFFFh
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Table 4.
Bank Sector
SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 Bank C SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230
PL127J Sector Architecture (Continued)
Sector Address (A22-A12)
11000000XXX 11000001XXX 11000010XXX 11000011XXX 11000100XXX 11000101XXX 11000110XXX 11000111XXX 11001000XXX 11001001XXX 11001010XXX 11001011XXX 11001100XXX 11001101XXX 11001110XXX 11001111XXX 11010000XXX 11010001XXX 11010010XXX 11010011XXX 11010100XXX 11010101XXX 11010110XXX 11010111XXX 11011000XXX 11011001XXX 11011010XXX 11011011XXX 11011100XXX 11011101XXX 11011110XXX 11011111XXX
Sector Size (Kwords)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Address Range (x16)
600000h-607FFFh 608000h-60FFFFh 610000h-617FFFh 618000h-61FFFFh 620000h-627FFFh 628000h-62FFFFh 630000h-637FFFh 638000h-63FFFFh 640000h-647FFFh 648000h-64FFFFh 650000h-657FFFh 658000h-65FFFFh 660000h-667FFFh 668000h-66FFFFh 670000h-677FFFh 678000h-67FFFFh 680000h-687FFFh 688000h-68FFFFh 690000h-697FFFh 698000h-69FFFFh 6A0000h-6A7FFFh 6A8000h-6AFFFFh 6B0000h-6B7FFFh 6B8000h-6BFFFFh 6C0000h-6C7FFFh 6C8000h-6CFFFFh 6D0000h-6D7FFFh 6D8000h-6DFFFFh 6E0000h-6E7FFFh 6E8000h-6EFFFFh 6F0000h-6F7FFFh 6F8000h-6FFFFFh
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Table 4.
Bank Sector
SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 Bank D SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269
PL127J Sector Architecture (Continued)
Sector Address (A22-A12)
11100000XXX 11100001XXX 11100010XXX 11100011XXX 11100100XXX 11100101XXX 11100110XXX 11100111XXX 11101000XXX 11101001XXX 11101010XXX 11101011XXX 11101100XXX 11101101XXX 11101110XXX 11101111XXX 11110000XXX 11110001XXX 11110010XXX 11110011XXX 11110100XXX 11110101XXX 11110110XXX 11110111XXX 11111000XXX 11111001XXX 11111010XXX 11111011XXX 11111100XXX 11111101XXX 11111110XXX 11111111000 11111111001 11111111010 11111111011 11111111100 11111111101 11111111110 11111111111
Sector Size (Kwords)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4
Address Range (x16)
700000h-707FFFh 708000h-70FFFFh 710000h-717FFFh 718000h-71FFFFh 720000h-727FFFh 728000h-72FFFFh 730000h-737FFFh 738000h-73FFFFh 740000h-747FFFh 748000h-74FFFFh 750000h-757FFFh 758000h-75FFFFh 760000h-767FFFh 768000h-76FFFFh 770000h-777FFFh 778000h-77FFFFh 780000h-787FFFh 788000h-78FFFFh 790000h-797FFFh 798000h-79FFFFh 7A0000h-7A7FFFh 7A8000h-7AFFFFh 7B0000h-7B7FFFh 7B8000h-7BFFFFh 7C0000h-7C7FFFh 7C8000h-7CFFFFh 7D0000h-7D7FFFh 7D8000h-7DFFFFh 7E0000h-7E7FFFh 7E8000h-7EFFFFh 7F0000h-7F7FFFh 7F8000h-7F8FFFh 7F9000h-7F9FFFh 7FA000h-7FAFFFh 7FB000h-7FBFFFh 7FC000h-7FCFFFh 7FD000h-7FDFFFh 7FE000h-7FEFFFh 7FF000h-7FFFFFh
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Table 5.
Bank Sector
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 Bank A SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 Bank B SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47
PL064J Sector Architecture
Sector Size (Kwords)
4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Sector Address (A22-A12)
0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 0000100XXX 0000101XXX 0000110XXX 0000111XXX 0001000XXX 0001001XXX 0001010XXX 0001011XXX 0001100XXX 0001101XXX 0001110XXX 0001111XXX 0010000XXX 0010001XXX 0010010XXX 0010011XXX 0010100XXX 0010101XXX 0010110XXX 0010111XXX 0011000XXX 0011001XXX 0011010XXX 0011011XXX 0011100XXX 0011101XXX 0011110XXX 0011111XXX 0100000XXX 0100001XXX 0100010XXX 0100011XXX 0100100XXX 0100101XXX 0100110XXX 0100111XXX 0101000XXX
Address Range (x16)
000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Table 5.
Bank Sector
SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 Bank B SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 Bank C SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 Bank C SA90 SA91 SA92 SA93 SA94 SA95
PL064J Sector Architecture (Continued)
Sector Address (A22-A12)
0101001XXX 0101010XXX 0101011XXX 0101100XXX 0101101XXX 0101110XXX 0101111XXX 0110000XXX 0110001XXX 0110010XXX 0110011XXX 0110100XXX 0110101XXX 0110110XXX 0110111XXX 0111000XXX 0111001XXX 0111010XXX 0111011XXX 0111100XXX 0111101XXX 0111110XXX 0111111XXX 1000000XXX 1000001XXX 1000010XXX 1000011XXX 1000100XXX 1000101XXX 1000110XXX 1000111XXX 1001000XXX 1001001XXX 1001010XXX 1001011XXX 1001100XXX 1001101XXX 1001110XXX 1001111XXX 1010000XXX 1010001XXX 1010010XXX 1010011XXX 1010100XXX 1010101XXX 1010110XXX 1010111XXX 1011000XXX
Sector Size (Kwords)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Address Range (x16)
148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh
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Table 5.
Bank Sector
SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 Bank C SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 Bank D SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141
PL064J Sector Architecture (Continued)
Sector Address (A22-A12)
1011001XXX 1011010XXX 1011011XXX 1011100XXX 1011101XXX 1011110XXX 1011111XXX 1100000XXX 1100001XXX 1100010XXX 1100011XXX 1100100XXX 1100101XXX 1100110XXX 1100111XXX 1101000XXX 1101001XXX 1101010XXX 1101011XXX 1101100XXX 1101101XXX 1101110XXX 1101111XXX 1110000XXX 1110001XXX 1110010XXX 1110011XXX 1110100XXX 1110101XXX 1110110XXX 1110111XXX 1111000XXX 1111001XXX 1111010XXX 1111011XXX 1111100XXX 1111101XXX 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111
Sector Size (Kwords)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4
Address Range (x16)
2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3F8FFFh 3F9000h-3F9FFFh 3FA000h-3FAFFFh 3FB000h-3FBFFFh 3FC000h-3FCFFFh 3FD000h-3FDFFFh 3FE000h-3FEFFFh 3FF000h-3FFFFFh
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Table 6.
Bank Sector
SA0 SA1 SA2 SA3 SA4 SA5 Bank A SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 Bank B SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
PL032J Sector Architecture
Sector Size (Kwords)
4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Sector Address (A22-A12)
000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001XXX 000010XXX 000011XXX 000100XXX 000101XXX 000110XXX 000111XXX 001000XXX 001001XXX 001010XXX 001011XXX 001100XXX 001101XXX 001110XXX 001111XXX 010000XXX 010001XXX 010010XXX 010011XXX 010100XXX 010101XXX 010110XXX 010111XXX 011000XXX 011001XXX 011010XXX 011011XXX 011100XXX 011101XXX 011110XXX 011111XXX
Address Range (x16)
000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh
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Table 6.
Bank Sector
SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 Bank C SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 Bank D SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77
PL032J Sector Architecture (Continued)
Sector Address (A22-A12)
100000XXX 100001XXX 100010XXX 100011XXX 100100XXX 100101XXX 100110XXX 100111XXX 101000XXX 101001XXX 101010XXX 101011XXX 101100XXX 101101XXX 101110XXX 101111XXX 110000XXX 110001XXX 110010XXX 110011XXX 110100XXX 110101XXX 110110XXX 110111XXX 111000XXX 111001XXX 111010XXX 111011XXX 111100XXX 111101XXX 111110XXX 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111
Sector Size (Kwords)
32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4
Address Range (x16)
100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1F8FFFh 1F9000h-1F9FFFh 1FA000h-1FAFFFh 1FB000h-1FBFFFh 1FC000h-1FCFFFh 1FD000h-1FDFFFh 1FE000h-1FEFFFh 1FF000h-1FFFFFh
Table 7.
Secured Silicon Sector Addresses
Sector Size Address Range 000000h-00003Fh 000040h-00007Fh
Factory-Locked Area Customer-Lockable Area
64 words 64 words
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Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on DQ7-DQ0. This mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system through the command register. When using programming equipment, the autoselect mode requires VID on address pin A9. Address pins must be as shown in Table 8 and Table 11. In addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see Table 3). Table 8 and Table 11 show the remaining address bits that are don't care. When all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on DQ7-DQ0. However, the autoselect codes can also be accessed insystem through the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 17. Note that if a Bank Address (BA) (on address bits PL127J: A22-A20, PL064J: A21-A19, PL032J: A20-A18) is asserted during the third write cycle of the autoselect command, the host system can read autoselect data that bank and then immediately read array data from the other bank, without exiting the autoselect mode. To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in Table 17. This method does not require V ID . Refer to the Autoselect Command Sequence for more information.
Table 8.
Description Manufacturer ID: Spansion products Read Cycle 1 Device ID Read Cycle 2 Read Cycle 3 Sector Protection Verification Secured Silicon Indicator Bit (DQ7, DQ6) CE# OE# WE#
Autoselect Codes (High Voltage Method)
A1 0 A9 A8 A7 A6 A5 to A4 X A3 A2 A1 A0 DQ15 to DQ0
Amax to A12 BA
L
L
H
X
VID
X
L
L
L
L
L
L
0001h
L
L
L
L
H
227Eh 2220h (PL127J) 2202h (PL064J) 220Ah (PL032J) 2200h (PL127J) 2201h (PL064J) 2201h (PL032J) 0001h (protected), 0000h (unprotected) 00C4h (factory and customer locked), 0084h (factory locked), 0004h (not locked)
L
L
H
BA
X
VID
X
L
L
L
H
H
H
L
L
H
H
H
H
L
L
H
SA
X
VID
X
L
L
L
L
L
H
L
L
L
H
BA
X
VID
X
X
L
X
L
L
H
H
Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don't care. Note: The autoselect codes may also be accessed in-system via command sequences
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Table 9.
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67-SA70 SA71-SA74 SA75-SA78 SA79-SA82 SA83-SA86 SA87-SA90 SA91-SA94 SA95-SA98 SA99-SA102 SA103-SA106 SA107-SA110 SA111-SA114 SA115-SA118 SA119-SA122 SA123-SA126 SA127-SA130
PL127J Boot Sector/Sector Block Addresses for Protection/Unprotection
Sector/ Sector Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords Sector SA131-SA134 SA135-SA138 SA139-SA142 SA143-SA146 SA147-SA150 SA151-SA154 SA155-SA158 SA159-SA162 SA163-SA166 SA167-SA170 SA171-SA174 SA175-SA178 SA179-SA182 SA183-SA186 SA187-SA190 SA191-SA194 SA195-SA198 SA199-SA202 SA203-SA206 SA207-SA210 SA211-SA214 SA215-SA218 SA219-SA222 SA223-SA226 SA227-SA230 SA231-SA234 SA235-SA238 SA239-SA242 SA243-SA246 SA247-SA250 SA251-SA254 SA255-SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 A22-A12 011111XXXXX 100000XXXXX 100001XXXXX 100010XXXXX 100011XXXXX 100100XXXXX 100101XXXXX 100110XXXXX 100111XXXXX 101000XXXXX 101001XXXXX 101010XXXXX 101011XXXXX 101100XXXXX 101101XXXXX 101110XXXXX 101111XXXXX 110000XXXXX 110001XXXXX 110010XXXXX 110011XXXXX 110100XXXXX 110101XXXXX 110110XXXXX 110111XXXXX 111000XXXXX 111001XXXXX 111010XXXXX 111011XXXXX 111100XXXXX 111101XXXXX 111110XXXXX 11111100XXX 11111101XXX 11111110XXX 11111111000 11111111001 11111111010 11111111011 Sector/ Sector Block Size 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords
A22-A12 00000000000 00000000001 00000000010 00000000011 00000000100 00000000101 00000000110 00000000111 00000001XXX 00000010XXX 00000011XXX 000001XXXXX 000010XXXXX 000011XXXXX 000100XXXXX 000101XXXXX 000110XXXXX 000111XXXXX 001000XXXXX 001001XXXXX 001010XXXXX 001011XXXXX 001100XXXXX 001101XXXXX 001110XXXXX 001111XXXXX 010000XXXXX 010001XXXXX 010010XXXXX 010011XXXXX 010100XXXXX 010101XXXXX 010110XXXXX 010111XXXXX 011000XXXXX 011001XXXXX 011010XXXXX 011011XXXXX 011100XXXXX 011101XXXXX 011110XXXXX
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Table 10.
Sector
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67-SA70 SA71-SA74 SA75-SA78 SA79-SA82 SA83-SA86 SA87-SA90 SA91-SA94 SA95-SA98 SA99-SA102 SA103-SA106 SA107-SA110 SA111-SA114 SA115-SA118 SA119-SA122 SA123-SA126 SA127-SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138
PL064J Boot Sector/Sector Block Addresses for Protection/Unprotection
A21-A12
0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001XXX 0000010XXX 0000011XXX 00001XXXXX 00010XXXXX 00011XXXXX 00100XXXXX 00101XXXXX 00110XXXXX 00111XXXXX 01000XXXXX 01001XXXXX 01010XXXXX 01011XXXXX 01100XXXXX 01101XXXXX 01110XXXXX 01111XXXXX 10000XXXXX 10001XXXXX 10010XXXXX 10011XXXXX 10100XXXXX 10101XXXXX 10110XXXXX 10111XXXXX 11000XXXXX 11001XXXXX 11010XXXXX 11011XXXXX 11100XXXXX 11101XXXXX 11110XXXXX 1111100XXX 1111101XXX 1111110XXX 1111111000 1111111001 1111111010 1111111011 1111111100
Sector/Sector Block Size
4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords
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Table 10.
Sector
SA139 SA140 SA141
PL064J Boot Sector/Sector Block Addresses for Protection/Unprotection
A21-A12
1111111101 1111111110 1111111111
Sector/Sector Block Size
4 Kwords 4 Kwords 4 Kwords
Table 11.
Sector
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11-SA14 SA15-SA18 SA19-SA22 SA23-SA26 SA27-SA30 SA31-SA34 SA35-SA38 SA39-SA42 SA43-SA46 SA47-SA50 SA51-SA54 SA55-SA58 SA59-SA62 SA63-SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77
PL032J Boot Sector/Sector Block Addresses for Protection/Unprotection
A21-A12
000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001XXX 000010XXX 000011XXX 0001XXXXX 0010XXXXX 0011XXXXX 0100XXXXX 0101XXXXX 0110XXXXX 0111XXXXX 1000XXXXX 1001XXXXX 1010XXXXX 1011XXXXX 1100XXXXX 1101XXXXX 1110XXXXX 111100XXX 111101XXX 111110XXX 111111000 111111001 111111010 111111011 111111100 111111101 111111110 111111111
Sector/Sector Block Size
4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 128 (4x32) Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords
Selecting a Sector Protection Mode
The device is shipped with all sectors unprotected. Optional Spansion programming services enable programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office for details. It is possible to determine whether a sector is protected or unprotected. See the Secured Silicon Sector Addresses for details.
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Table 12.
DYB PPB PPB Lock
Sector Protection Schemes
Sector State
0 0 0 1 1 0 1 1
0 0 1 0 1 1 0 1
0 1 0 0 0 1 1 1
Unprotected--PPB and DYB are changeable Unprotected--PPB not changeable, DYB is changeable
Protected--PPB and DYB are changeable
Protected--PPB not changeable, DYB is changeable
Sector Protection
The PL127J, PL064J, and PL032J features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups.
Sector Protection Schemes
Password Sector Protection
A highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted
WP# Hardware Protection
A write protect pin that can prevent program or erase operations in sectors SA1133, SA1-134, SA2-0 and SA2-1. The WP# Hardware Protection feature is always available, independent of the software managed protection method chosen.
Selecting a Sector Protection Mode
All parts default to operate in the Persistent Sector Protection mode. The customer must then choose if the Persistent or Password Protection method is most desirable. There are two one-time programmable non-volatile bits that define which sector protection method will be used. If the Persistent Sector Protection method is desired, programming the Persistent Sector Protection Mode Locking Bit permanently sets the device to the Persistent Sector Protection mode. If the Password Sector Protection method is desired, programming the Password Mode Locking Bit permanently sets the device to the Password Sector Protection mode. It is not possible to switch between the two protection modes once a locking bit has been set. One of the two modes must be selected when the device is first programmed. This prevents a program or virus from later setting the Password Mode Locking Bit, which would cause an unexpected shift from the default Persistent Sector Protection Mode into the Password Protection Mode. The device is shipped with all sectors unprotected. Optional Spansion programming services enable programming and protecting sectors at the factory prior to shipping the device. Contact your local sales office for details.
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It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details.
Persistent Sector Protection
The Persistent Sector Protection method replaces the 12 V controlled protection method in previous flash devices. This new method provides three different sector protection states: Persistently Locked--The sector is protected and cannot be changed. Dynamically Locked--The sector is protected and can be changed by a simple command. Unlocked--The sector is unprotected and can be changed by a simple command. To achieve these states, three types of "bits" are used: Persistent Protection Bit Persistent Protection Bit Lock Persistent Sector Protection Mode Locking Bit
Persistent Protection Bit (PPB)
A single Persistent (non-volatile) Protection Bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). All 4 Kword boot-block sectors have individual sector Persistent Protection Bits (PPBs) for greater flexibility. Each PPB is individually modifiable through the PPB Write Command. The device erases all PPBs in parallel. If any PPB requires erasure, the device must be instructed to preprogram all of the sector PPBs prior to PPB erasure. Otherwise, a previously erased sector PPBs can potentially be over-erased. The flash device does not have a built-in means of preventing sector PPBs over-erasure.
Persistent Protection Bit Lock (PPB Lock)
The Persistent Protection Bit Lock (PPB Lock) is a global volatile bit. When set to "1", the PPBs cannot be changed. When cleared ("0"), the PPBs are changeable. There is only one PPB Lock bit per device. The PPB Lock is cleared after powerup or hardware reset. There is no command sequence to unlock the PPB Lock. Dynamic Protection Bit (DYB) A volatile protection bit is assigned for each sector. After power-up or hardware reset, the contents of all DYBs is "0". Each DYB is individually modifiable through the DYB Write Command. When the parts are first shipped, the PPBs are cleared, the DYBs are cleared, and PPB Lock is defaulted to power up in the cleared state - meaning the PPBs are changeable. When the device is first powered on the DYBs power up cleared (sectors not protected). The Protection State for each sector is determined by the logical OR of the PPB and the DYB related to that sector. For the sectors that have the PPBs cleared, the DYBs control whether or not the sector is protected or unprotected. By issuing the DYB Write command sequences, the DYBs will be set or cleared, thus placing each sector in the protected or unprotected state. These are the socalled Dynamic Locked or Unlocked states. They are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. This allows software to easily protect sectors against in-
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advertent changes yet does not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level of protection. The PPBs retain their state across power cycles because they are non-volatile. Individual PPBs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. The PPBs are also limited to 100 erase cycles. The PPB Lock bit adds an additional level of protection. Once all PPBs are programmed to the desired settings, the PPB Lock may be set to "1". Setting the PPB Lock disables all program and erase commands to the non-volatile PPBs. In effect, the PPB Lock Bit locks the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. System boot code can determine if any changes to the PPB are needed; for example, to allow new system code to be downloaded. If no changes are needed then the boot code can set the PPB Lock to disable any further changes to the PPBs during system operation. The WP#/ACC write protect pin adds a final level of hardware protection to sectors SA1-133, SA1-134, SA2-0 and SA2-1. When this pin is low it is not possible to change the contents of these sectors. These sectors generally hold system boot code. The WP#/ACC pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. For customers who are concerned about malicious viruses there is another level of security - the persistently locked state. To persistently protect a given sector or sector group, the PPBs associated with that sector need to be set to "1". Once all PPBs are programmed to the desired settings, the PPB Lock should be set to "1". Setting the PPB Lock automatically disables all program and erase commands to the Non-Volatile PPBs. In effect, the PPB Lock "freezes" the PPBs into their current state. The only way to clear the PPB Lock is to go through a power cycle. It is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. The sectors in the dynamic state are all unprotected. If there is a need to protect some of them, a simple DYB Write command sequence is all that is necessary. The DYB write command for the dynamic sectors switch the DYBs to signify protected and unprotected, respectively. If there is a need to change the status of the persistently locked sectors, a few more steps are required. First, the PPB Lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. The PPBs can then be changed to reflect the desired settings. Setting the PPB lock bit once again will lock the PPBs, and the device operates normally again. The best protection is achieved by executing the PPB lock bit set command early in the boot code, and protect the boot code by holding WP#/ACC = VIL. Table 12 contains all possible combinations of the DYB, PPB, and PPB lock relating to the status of the sector. In summary, if the PPB is set, and the PPB lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the PPB lock. If the PPB is cleared, the sector can be dynamically locked or unlocked. The DYB then controls whether or not the sector is protected or unprotected. If the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. A program command to a protected sector enables status polling for approximately 1 s before the device returns to read
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mode without having modified the contents of the protected sector. An erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sector. The programming of the DYB, PPB, and PPB lock for a given sector can be verified by writing a DYB/PPB/PPB lock verify command to the device. There is an alternative means of reading the protection status. Take RESET# to VIL and hold WE# at VIH.(The high voltage A9 Autoselect Mode also works for reading the status of the PPBs). Scanning the addresses (A18-A11) while (A6, A1, A0) = (0, 1, 0) will produce a logical `1" code at device output DQ0 for a protected sector or a "0" for an unprotected sector. In this mode, the other addresses are don't cares. Address location with A1 = VIL are reserved for autoselect manufacturer and device codes.
Persistent Sector Protection Mode Locking Bit
Like the password mode locking bit, a Persistent Sector Protection mode locking bit exists to guarantee that the device remain in software sector protection. Once set, the Persistent Sector Protection locking bit prevents programming of the password protection mode locking bit. This guarantees that a hacker could not place the device in password protection mode.
Password Protection Mode
The Password Sector Protection Mode method allows an even higher level of security than the Persistent Sector Protection Mode. There are two main differences between the Persistent Sector Protection and the Password Sector Protection Mode: When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the locked state, rather than cleared to the unlocked state. The only means to clear the PPB Lock bit is by writing a unique 64-bit Password to the device. The Password Sector Protection method is otherwise identical to the Persistent Sector Protection method. A 64-bit password is the only additional tool utilized in this method. Once the Password Mode Locking Bit is set, the password is permanently set with no means to read, program, or erase it. The password is used to clear the PPB Lock bit. The Password Unlock command must be written to the flash, along with a password. The flash device internally compares the given password with the pre-programmed password. If they match, the PPB Lock bit is cleared, and the PPBs can be altered. If they do not match, the flash device does nothing. There is a built-in 2 s delay for each "password check." This delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password.
Password and Password Mode Locking Bit
In order to select the Password sector protection scheme, the customer must first program the password. The password may be correlated to the unique Electronic Serial Number (ESN) of the particular flash device. Each ESN is different for every flash device; therefore each password should be different for every flash device. While programming in the password region, the customer may perform Password Verify operations.
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Once the desired password is programmed in, the customer must then set the Password Mode Locking Bit. This operation achieves two objectives: Permanently sets the device to operate using the Password Protection Mode. It is not possible to reverse this function. Disables all further commands to the password region. All program, and read operations are ignored. Both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. The user must be sure that the Password Protection method is desired when setting the Password Mode Locking Bit. More importantly, the user must be sure that the password is correct when the Password Mode Locking Bit is set. Due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. If the password is lost after setting the Password Mode Locking Bit, there will be no way to clear the PPB Lock bit. The Password Mode Locking Bit, once set, prevents reading the 64-bit password on the DQ bus and further password programming. The Password Mode Locking Bit is not erasable. Once Password Mode Locking Bit is programmed, the Persistent Sector Protection Locking Bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed.
64-bit Password
The 64-bit Password is located in its own memory space and is accessible through the use of the Password Program and Verify commands (see "Password Verify Command"). The password function works in conjunction with the Password Mode Locking Bit, which when set, prevents the Password Verify command from reading the contents of the password on the pins of the device.
Write Protect (WP#)
The Write Protect feature provides a hardware method of protecting the upper two and lower two sectors without using VID. This function is provided by the WP# pin and overrides the previously discussed High Voltage Sector Protection method. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two outermost 4 Kword sectors on both ends of the flash array independent of whether it was previously protected or unprotected. If the system asserts VIH on the WP#/ACC pin, the device reverts the upper two and lower two sectors to whether they were last set to be protected or unprotected. That is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in the High Voltage Sector Protection. Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.
Persistent Protection Bit Lock
The Persistent Protection Bit (PPB) Lock is a volatile bit that reflects the state of the Password Mode Locking Bit after power-up reset. If the Password Mode Lock Bit is also set after a hardware reset (RESET# asserted) or a power-up reset, the ONLY means for clearing the PPB Lock Bit in Password Protection Mode is to issue the Password Unlock command. Successful execution of the Password Unlock command clears the PPB Lock Bit, allowing for sector PPBs modifications. Asserting RESET#, taking the device through a power-on reset, or issuing the PPB Lock
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Bit Set command sets the PPB Lock Bit to a "1" when the Password Mode Lock Bit is not set. If the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the PPB Lock Bit Set command. Once set the only means for clearing the PPB Lock Bit is by issuing a hardware or power-up reset. The Password Unlock command is ignored in Persistent Protection Mode.
High Voltage Sector Protection
Sector protection and unprotection may also be implemented using programming equipment. The procedure requires high voltage (VID) to be placed on the RESET# pin. Refer to Figure 1 for details on this procedure. Note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle.
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START PLSCNT = 1 RESET# = VID Wait 4 s
Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address
START PLSCNT = 1 RESET# = VID Wait 4 s
Temporary Sector Unprotect Mode
No
First Write Cycle = 60h?
Yes
First Write Cycle = 60h?
No
Temporary Sector Unprotect Mode
Yes
Set up sector address
No
All sectors protected?
Yes
Sector Protect: Write 60h to sector address with A7-A0 = 00000010
Wait 100 s
Verify Sector Protect: Write 40h to sector address with A7-A0 = 00000010 Read from sector address with A7-A0 = 00000010
No
Set up first sector address
Sector Unprotect: Write 60h to sector address with A7-A0 = 01000010
Reset PLSCNT = 1
Increment PLSCNT
Wait 1.2 ms
Verify Sector Unprotect: Write 40h to sector address with A7-A0 = 00000010
Increment PLSCNT
No
PLSCNT = 25? Yes
Remove VID from RESET#
Data = 01h?
Yes
No
Read from sector address with A7-A0 = 00000010
Set up next sector address
Yes
Protect another sector?
PLSCNT = 1000? Yes
Remove VID from RESET#
No Data = 00h? Yes
Write reset command
No
Remove VID from RESET#
Sector Protect complete
Last sector verified?
Yes
No
Write reset command
Device failed
Write reset command Sector Unprotect complete
Sector Protect complete
Remove VID from RESET#
Sector Protect Algorithm
Write reset command
Device failed
Sector Unprotect complete
Sector Unprotect Algorithm
Figure 1. In-System Sector Protection/Sector Unprotection Algorithms
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Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again. 2 shows the algorithm, and 21 shows the timing diagrams, for this feature. While PPB lock is set, the device cannot enter the Temporary Sector Unprotection Mode.
START
RESET# = VID (Note 1) Perform Erase or Program Operations
RESET# = VIH
Temporary Sector Unprotect Completed (Note 2)
Notes: 1. All protected sectors unprotected (If WP#/ACC = VIL, upper two and lower two sectors will remain protected). 2. All previously protected sectors are protected once again
Figure 2.
Temporary Sector Unprotect Operation
Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN) The 128-word Secured Silicon sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. The Secured Silicon sector is located at addresses 000000h-00007Fh in both Persistent Protection mode and Password Protection mode. It uses indicator bits (DQ6, DQ7) to indicate the factory-locked and customer-locked status of the part. The system accesses the Secured Silicon Sector through a command sequence (see the Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence). After the system has written the Enter Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the normal address space. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled.
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Factory-Locked Area (64 words)
The factory-locked area of the Secured Silicon Sector (000000h-00003Fh) is locked when the part is shipped, whether or not the area was programmed at the factory. The Secured Silicon Sector Factory-locked Indicator Bit (DQ7) is permanently set to a "1". Optional Spansion programming services can program the factory-locked area with a random ESN, a customer-defined code, or any combination of the two. Because only Spansion can program and protect the factorylocked area, this method ensures the security of the ESN once the product is shipped to the field. Contact your local sales office for details on using Spansion's programming services. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon sector is enabled.
Customer-Lockable Area (64 words)
The customer-lockable area of the Secured Silicon Sector (000040h-00007Fh) is shipped unprotected, which allows the customer to program and optionally lock the area as appropriate for the application. The Secured Silicon Sector Customerlocked Indicator Bit (DQ6) is shipped as "0" and can be permanently locked to "1" by issuing the Secured Silicon Protection Bit Program Command. The Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the Secured Silicon Sector. The Customer-lockable Secured Silicon Sector area can be protected using one of the following procedures: Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 1, except that RESET# may be at either VIH or VID. This allows in-system protection of the Secured Silicon Sector Region without raising any device pin to a high voltage. Note that this method is only applicable to the Secured Silicon Sector. To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm shown in Figure 3. Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector Region command sequence to return to reading and writing the remainder of the array. The Secured Silicon Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way.
Secured Silicon Sector Protection Bits
The Secured Silicon Sector Protection Bits prevent programming of the Secured Silicon Sector memory area. Once set, the Secured Silicon Sector memory area contents are non-modifiable.
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START RESET# = VIH or VID Wait 1 s Write 60h to any address If data = 00h, SecSi Sector is unprotected. If data = 01h, SecSi Sector is protected.
Remove VIH or VID from RESET#
Write 40h to SecSi Sector address with A6 = 0, A1 = 1, A0 = 0 Read from SecSi Sector address with A6 = 0, A1 = 1, A0 = 0
Write reset command SecSi Sector Protect Verify complete
Figure 3.
Secured Silicon Sector Protect Verify
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Write Pulse "Glitch" Protection
Noise pulses of less than 3 ns (typical) on OE#, CE#, or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
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Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 13-16. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 13-16. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100. Contact your local sales office for copies of these documents.
Table 13. CFI Query Identification String
Addresses 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Query Unique ASCII string "QRY" Description
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
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Table 14.
Addresses 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0003h 0000h 0009h 0000h 0004h 0000h 0004h 0000h
System Interface String
Description
VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 15.
Addresses 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0018h (PL127J) 0017h (PL064J) 0016h (PL032J) 0001h 0000h 0000h 0000h 0003h 0007h 0000h 0020h 0000h 00FDh (PL127J) 007Dh (PL064J) 003Dh (PL032J) 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h
Device Geometry Definition
Description
Device Size = 2N byte Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 3 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 4 Information (refer to the CFI specification or CFI publication 100)
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Table 16.
Addresses 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0033h TBD
Primary Vendor-Specific Extended Query
Description Query-unique ASCII string "PRI" Major version number, ASCII (reflects modifications to the silicon) Minor version number, ASCII (reflects modifications to the CFI table) Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Silicon Revision Number (Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 07 = Advanced Sector Protection Simultaneous Operation 00 = Not Supported, X = Number of Sectors excluding Bank 1 Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 00h = Uniform device, 01h = Both top and bottom boot with write protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and Bottom Program Suspend 0 = Not supported, 1 = Supported Bank Organization 00 = Data at 4Ah is zero, X = Number of Banks Bank 1 Region Information X = Number of Sectors in Bank 1 Bank 2 Region Information X = Number of Sectors in Bank 2 Bank 3 Region Information X = Number of Sectors in Bank 3
46h 47h 48h 49h
0002h 0001h 0001h 0007h (PLxxxJ) 00E7h (PL127J) 0077h (PL064J) 003Fh (PL032J) 0000h 0002h (PLxxxJ) 0085h 0095h
4Ah
4Bh 4Ch 4Dh 4Eh
4Fh
0001h
50h 57h
0001h 0004h 0027h (PL127J) 0017h (PL064J) 000Fh (PL032J) 0060h (PL127J) 0030h (PL064J) 0018h (PL032J) 0060h (PL127J) 0030h (PL064J) 0018h (PL032J)
58h
59h
5Ah
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Table 16.
Addresses 5Bh Data
Primary Vendor-Specific Extended Query (Continued)
Description Bank 4 Region Information X = Number of Sectors in Bank 4
0027h (PL127J) 0017h (PL064J) 000Fh (PL032J)
Command Definitions
Writing specific address and data commands or sequences into the command register initiates device operations. Table 17 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristic section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erasesuspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The AC Characteristic table provides the read parameters, and Figure 12 shows the timing diagram.
Reset Command
Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete.
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The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Table 17 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 3 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erasesuspend-read mode if the bank was previously in Erase Suspend).
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence
The Secured Silicon Sector region provides a secured data area containing a random, eight word electronic serial number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence returns the device to normal operation. The Secured Silicon Sector is not accessible when the device is executing an Embedded Program or embedded Erase algorithm. Table 17 shows the address and data requirements for both command sequences. See also "Secured Silicon Sector Flash Memory Region" for further information. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 17 shows the address and data requirements for the program command sequence. Note that the Secured
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Silicon Sector, autoselect, and CFI functions are unavailable when a [program/ erase] operation is in progress. When the Embedded Program algorithm is complete, that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Note that the Secured Silicon Sector, autoselect and CFI functions are unavailable when the Secured Silicon Sector is enabled. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1."
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program data to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Table 17 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. (See Table 18) The device offers accelerated program operations through the WP#/ACC pin. When the system asserts VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH any operation other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. 4 illustrates the algorithm for the program operation. Refer to the Erase/Program Operations table in the AC Characteristics section for parameters, and Figure 14 for timing diagrams.
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START
Write Program Command Sequence
Embedded Program algorithm in progress
Data Poll from System
Verify Data?
No
Yes No
Increment Address
Last Address?
Yes Programming Completed
Note: See Table 17 for program command sequence.
Figure 4.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 17 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. Note that Secured Silicon Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity.
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5 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the AC Characteristics section for parameters, and Figure 16 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 17 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise erasure may begin. Any sector erase address and command following the exceeded timeout may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets that bank to the read mode. The system must rewrite the command sequence and any additional addresses and commands. Note that Secured Silicon Sector, autoselect, and CFI functions are unavailable when a [program/ erase] operation is in progress. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. 5 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the AC Characteristics section for parameters, and Figure 16 section for timing diagrams.
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START
Write Erase Command Sequence (Notes 1, 2)
Data Poll to Erasing Bank from System
Embedded Erase algorithm in progress
No
Data = FFh?
Yes Erasure Completed
Notes: 1. See Table 17 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer.
Figure 5.
Erase Operation
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. The bank address is required when writing this command. This command is valid only during the sector erase operation, including the 80 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a maximum of 35 s to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. Addresses are "don't-cares" when writing the Erase suspend command. After the erase operation has been suspended, the bank enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. The system can determine the status of the program
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operation using the DQ7 or DQ6 status bits, just as in the standard Word Program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. Refer to the Secured Silicon Sector Addresses and the Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command (address bits are don't care). The bank address of the erase-suspended bank is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. If the Persistent Sector Protection Mode Locking Bit is verified as programmed without margin, the Persistent Sector Protection Mode Locking Bit Program Command should be reissued to improve program margin. If the Secured Silicon Sector Protection Bit is verified as programmed without margin, the Secured Silicon Sector Protection Bit Program Command should be reissued to improve program margin. After programming a PPB, two additional cycles are needed to determine whether the PPB has been programmed with margin. If the PPB has been programmed without margin, the program command should be reissued to improve the program margin. Also note that the total number of PPB program/ erase cycles is limited to 100 cycles. Cycling the PPBs beyond 100 cycles is not guaranteed. After erasing the PPBs, two additional cycles are needed to determine whether the PPB has been erased with margin. If the PPBs has been erased without margin, the erase command should be reissued to improve the program margin. The programming of either the PPB or DYB for a given sector or sector group can be verified by writing a Sector Protection Status command to the device. Note that there is no single command to independently verify the programming of a DYB for a given sector group.
Command Definitions Tables
Table 17.
Command (Notes)
Read (Note 5) Reset (Note 6) Manufacturer ID Device ID (Note 10) Secured Silicon Sector Factory Protect (Note 8) Sector Group Protect Verify (Note 9) Program Chip Erase Sector Erase Program/Erase Suspend (Note 11) Cycles Addr RA XXX 555 555 555 555 555 555 555 BA
Memory Array Command Definitions
Bus Cycles (Notes 1-4) Data RD F0 AA AA AA AAA AA AA AA B0 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 (BA) 555 (BA) 555 (BA) 555 (BA) 555 555 555 555 90 90 90 90 A0 80 80 (BA) X00 (BA) X01 X03 (SA) X02 PA 555 555 01 227E (Note 8) XX00/ XX01 PD AA AA 2AA 2AA 55 55 555 SA 10 30 (BA) X0E (Note 10) (BA) X0F (Note 10) Addr Data Addr Data Addr Data Addr Data Addr Data
1 1 4 6 4 4 4 6 6 1
Autoselect (Note 7)
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Table 17.
Command (Notes)
Program/Erase Resume (Note 12) CFI Query (Note 13) Accelerated Program (Note 15) Unlock Bypass Entry (Note 15) Unlock Bypass Program (Note 15) Unlock Bypass Erase (Note 15) Unlock Bypass CFI (Notes 13, 15) Unlock Bypass Reset (Note 15) Cycles Addr BA 55 XX 555 XX XX XX XXX
Memory Array Command Definitions
Bus Cycles (Notes 1-4) Data 30 98 A0 AA A0 80 98 90 XXX 00 PA 2AA PA XX PD 55 PD 10 555 20 Addr Data Addr Data Addr Data Addr Data Addr Data
1 1 2 3 2 2 1 2
Legend: BA = Address of bank switching to autoselect mode, bypass mode, or erase operation. Determined by PL127J: Amax:A20, PL064J: Amax:A19, PL032J: Amax:A18. PA = Program Address (Amax:A0). Addresses latch on falling edge of WE# or CE# pulse, whichever happens later. PD = Program Data (DQ15:DQ0) written to location PA. Data latches on rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells in table denote read cycles. All other cycles are write operations. 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don't cares. 5. No unlock or command cycles required when bank is reading array data. 6. The Reset command is required to return to reading array (or to erase-suspend-read mode if previously in Erase Suspend) when bank is in autoselect mode, or if DQ5 goes high (while bank is providing status information). 7. Fourth cycle of autoselect command sequence is a read cycle. System must provide bank address to obtain manufacturer ID or device ID information. See Autoselect Command Sequence section for more information. 8. The data is C4h for factory and customer locked, 84h for factory locked and 04h for not locked.
RA = Read Address (Amax:A0). RD = Read Data (DQ15:DQ0) from location RA. SA = Sector Address (Amax:A12) for verifying (in autoselect mode) or erasing. WD = Write Data. See "Configuration Register" definition for specific write data. Data latched on rising edge of WE#. X = Don't care
9. The data is 00h for an unprotected sector group and 01h for a protected sector group. 10. Device ID must be read across cycles 4, 5, and 6. PL127J (X0Eh = 2220h, X0Fh = 2200h),PL064J (X0Eh = 2202h, X0Fh = 2201h), PL032J (X0Eh = 220Ah, X0Fh = 2201h). 11. System may read and program in non-erasing sectors, or enter autoselect mode, when in Program/Erase Suspend mode. Program/Erase Suspend command is valid only during a sector erase operation, and requires bank address. 12. Program/Erase Resume command is valid only during Erase Suspend mode, and requires bank address. 13. Command is valid when device is ready to read array data or when device is in autoselect mode. 14. WP#/ACC must be at VID during the entire operation of command. 15. Unlock Bypass Entry command is required prior to any Unlock Bypass operation. Unlock Bypass Reset command is required to return to the reading array.
Table 18.
Command (Notes) Reset Secured Silicon Sector Entry Secured Silicon Sector Exit Cycles Addr XXX 555 555 Data F0 AA AA 2AA 2AA 55 55 Addr
Sector Protection Command Definitions
Bus Cycles (Notes 1-4) Addr Data Addr Data Addr Data Addr Data
Data Addr Data
1 3 4
555 555
88 90 XX 00
Secured Silicon Protection Bit 6 Program (Notes 5, 6) Secured Silicon Protection Bit Status 5
555
AA
2AA
55
555
60
OW
68
OW
48
OW
RD(0)
555 555
AA AA
2AA 2AA
55 55
555 555
60 38
OW XX[0-3]
48 PD[0-3]
OW
RD(0)
Password Program 4 (Notes 5, 7, 8)
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Table 18.
Password Verify (Notes 6, 8, 9) Password Unlock (Notes 7, 10, 11) PPB Program (Notes 5, 6, 12) PPB Status All PPB Erase (Notes 5, 6, 13, 14) PPB Lock Bit Set PPB Lock Bit Status (Note 15) DYB Write (Note 7) DYB Erase (Note 7) DYB Status (Note 6) PPMLB Program (Notes 5, 6, 12) PPMLB Status (Note 5) SPMLB Program (Notes 5, 6, 12) SPMLB Status (Note 5) 4 7 6 4 6 3 4 4 4 4 6 5 6 5 555 555 555 555 555 555 555 555 555 555 555 555 555 555 AA AA AA AA AA AA AA AA AA AA AA AA AA AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 55 55 55 55 55 55 55
Sector Protection Command Definitions
555 555 555 555 555 555 555 555 555 555 555 555 555 555 C8 28 60 90 60 78 58 48 48 58 60 60 60 60 SA SA SA SA PL PL SL SL RD(1) X1 X0 RD(0) 68 48 68 48 PL PL SL SL 48 RD(0) 48 RD(0) SL RD(0) PL RD(0) PWA[0-3] PWD[0-3] PWA[0] (SA)WP (SA)WP WP PWD[0] 68 RD(0) 60 (SA) 40 (SA)WP RD(0) PWA[1] PWD[1] PWA[2] PWD[2] PWA[3] PWD[3] (SA)WP 48 (SA)WP RD(0)
Legend: DYB = Dynamic Protection Bit OW = Address (A7:A0) is (00011010) PD[3:0] = Password Data (1 of 4 portions) PPB = Persistent Protection Bit PWA = Password Address. A1:A0 selects portion of password. PWD = Password Data being verified. PL = Password Protection Mode Lock Address (A7:A0) is (00001010)
Notes: 1. See Table 1 for description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells in table denote read cycles. All other cycles are write operations. 4. During unlock and command cycles, when lower address bits are 555 or 2AAh as shown in table, address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are don't cares. 5. The reset command returns device to reading array. 6. Cycle 4 programs the addressed locking bit. Cycles 5 and 6 validate bit has been fully programmed when DQ0 = 1. If DQ0 = 0 in cycle 6, program command must be issued and verified again. 7. Data is latched on the rising edge of WE#. 8. Entire command sequence must be entered for each portion of password.
RD(0) = Read Data DQ0 for protection indicator bit. RD(1) = Read Data DQ1 for PPB Lock status. SA = Sector Address where security command applies. Address bits Amax:A12 uniquely select any sector. SL = Persistent Protection Mode Lock Address (A7:A0) is (00010010) WP = PPB Address (A7:A0) is (00000010) X = Don't care PPMLB = Password Protection Mode Locking Bit SPMLB = Persistent Protection Mode Locking Bit 9. Command sequence returns FFh if PPMLB is set. 10. The password is written over four consecutive cycles, at addresses 0-3. 11. A 2 s timeout is required between any two portions of password. 12. A 100 s timeout is required between cycles 4 and 5. 13. A 1.2 ms timeout is required between cycles 4 and 5. 14. Cycle 4 erases all PPBs. Cycles 5 and 6 validate bits have been fully erased when DQ0 = 0. If DQ0 = 1 in cycle 6, erase command must be issued and verified again. Before issuing erase command, all PPBs should be programmed to prevent PPB overerasure. 15. DQ1 = 1 if PPB locked, 0 if unlocked.
Write Operation Status
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 19 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. The device also provides a
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hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then that bank returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the bank enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 400 s, then the bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ15-DQ0 on the following read cycles. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ15-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ15-DQ0 may be still invalid. Valid data on DQ15-DQ0 will appear on successive read cycles. Table 19 shows the outputs for Data# Polling on DQ7. 6 shows the Data# Polling algorithm. 18 in the AC Characteristic section shows the Data# Polling timing diagram.
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START
Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 6. Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-suspend-read mode. Table 19 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge
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of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 400 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 19 shows the outputs for Toggle Bit I on DQ6. Figure 7 shows the toggle bit algorithm. Figure 19 in "Read Operation Timings" shows the toggle bit timing diagrams. Figure 20 shows the differences between DQ2 and DQ6 in graphical form. See also the DQ2: Toggle Bit II.
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START
Read Byte (DQ7-DQ0) Address =VA Read Byte (DQ7-DQ0) Address =VA
Toggle Bit = Toggle?
No
Yes
No
DQ5 = 1?
Yes
Read Byte Twice (DQ7-DQ0) Address = VA
Toggle Bit = Toggle?
No
Yes
Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Note: The system should recheck the toggle bit even if DQ5 = "1" because the toggle bit may stop toggling as DQ5 changes to "1." See the DQ6: Toggle Bit I and DQ2: Toggle Bit II for more information.
Figure 7.
Toggle Bit Algorithm
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 19 to compare outputs for DQ2 and DQ6. Figure 7 shows the toggle bit algorithm in flowchart form, and the DQ2: Toggle Bit II explains the algorithm. See also the DQ6: Toggle Bit I. Figure 19 shows the toggle bit timing diagram. Figure 20 shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and
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store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 7).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1." Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." See also the Sector Erase Command Sequence. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 19 shows the status of DQ3 relative to the other status bits.
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Table 19. Write Operation Status
Status Standard Mode Embedded Program Algorithm Embedded Erase Algorithm Erase-SuspendRead Erase Suspended Sector Non-Erase Suspended Sector DQ7 (Note 2) DQ7# 0 1 Data DQ7# DQ6 Toggle Toggle No toggle Data Toggle DQ5 (Note 1) 0 0 0 Data 0 DQ3 N/A 1 N/A Data N/A DQ2 (Note 2) No toggle Toggle Toggle Data N/A RY/BY# 0 0 1 1 0
Erase Suspend Mode
Erase-Suspend-Program
Notes: 1. DQ5 switches to `1' when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.
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Absolute Maximum Ratings
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +4.0 V RESET# (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +13.0 V WP#/ACC (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +10.5 V All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3). . . . . . . . . . . . . . . . . . . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8. 2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is -0.5 V. During voltage transitions, A9, OE#, WP#/ACC, and RESET# may overshoot VSS to -2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on pin A9, OE#, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is +9.5 V which may overshoot to +12.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. 4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
20 ns +0.8 V -0.5 V -2.0 V 20 ns
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns
20 ns
20 ns
Maximum Negative Overshoot Waveform
Maximum Positive Overshoot Waveform
Figure 8.
Maximum Overshoot Waveforms
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Operating Ranges
Operating ranges define those limits between which the functionality of the device is guaranteed.
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
Wireless Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C
Supply Voltages
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.7-3.1 V VIO (see Note) . . 1.65-1.95 V (for PL127J) or 2.7-3.1 V (for all PLxxxJ devices)
Notes: For all AC and DC specifications, VIO = VCC; contact your local sales office for other VIO options.
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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DC Characteristics
Table 20.
Parameter Symbol ILI ILIT ILR ILO ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 ICC8 ICC9 VIL VIH VHH VID Parameter Description Input Load Current A9, OE#, RESET# Input Load Current Reset Leakage Current Output Leakage Current VCC Active Read Current (Notes 1, 2) VCC Active Write Current (Notes 2, 3) VCC Standby Current (Note 2) VCC Reset Current (Note 2) Automatic Sleep Mode (Notes 2, 4) VCC Active Read-While-Program Current (Notes 1, 2) VCC Active Read-While-Erase Current (Notes 1, 2) VCC Active Program-While-EraseSuspended Current (Notes 2, 5) VCC Active Page Read Current (Note 2) Input Low Voltage
CMOS Compatible
Test Conditions Min Typ Max 1.0 35 35 1.0 5 MHz 10 MHz 15 45 15 0.2 0.2 0.2 5 MHz 10 MHz 5 MHz 10 MHz 21 46 21 46 17 10 -0.4 -0.5 VIO-0.4 2.0 8.5 11.5 25 55 25 5 5 5 45 70 45 70 25 15 0.4 0.8 VIO+0.4 VCC+0.3 9.5 12.5 0.1 0.4 VIO-0.1 2.4 2.3 2.5 Unit A A A A mA mA A A A mA
VIN = VSS to VCC, VCC = VCC max VCC = VCC max; VID= 12.5 V VCC = VCC max; VID= 12.5 V VOUT = VSS to VCC, OE# = VIH VCC = VCC max OE# = VIH, VCC = VCC max (Note 1) OE# = VIH, WE# = VIL CE#, RESET#, WP#/ACC = VIO 0.3 V RESET# = VSS 0.3 V VIH = VIO 0.3 V; VIL = VSS 0.3 V OE# = VIH, OE# = VIH, OE# = VIH OE# = VIH, 8 word Page Read VIO = 1.65-1.95 V (PL127J) VIO = 2.7-3.6 V VIO = 1.65-1.95 V (PL127J) VIO = 2.7-3.6 V VCC = 3.0 V 10% VCC = 3.0 V 10% IOL = 100 A, VCC = VCC min, VIO = 1.65- 1.95 V (PL127J) IOL = 2.0 mA, VCC = VCC min, VIO = 2.7-3.6 V IOH = -100 A, VCC = VCC min, VIO = 1.65- 1.95 V (PL127J) IOH = -2.0 mA, VCC = VCC min, VIO = 2.7-3.6 V
mA mA mA V V V V V V V V V V V
Input High Voltage Voltage for ACC Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect
VOL
Output Low Voltage
VOH
Output High Voltage
VLKO
Low VCC Lock-Out Voltage (Note 5)
Notes: 1. The ICC current listed is typically less than 5 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCCmax. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 1 mA. 5. Not 100% tested. 6. Valid CE1#/CE2# conditions: (CE1# = VIL, CE2# = VIH,) or (CE1# = VIH, CE2# = VIL) or (CE1# = VIH, CE2# = VIH)
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
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AC Characteristic
Test Conditions
3.6 V
Device Under Test CL 6.2 k
2.7 k
Device Under Test CL
VIO = 3.0 V Note: Diodes are IN3064 or equivalent
VIO = 1.8 V (PL127J)
Figure 9. Table 21.
Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) Input Rise and Fall Times
Test Setups
Test Specifications
All Speeds 1 TTL gate 30 VIO = 1.8 V (PL127J) VIO = 3.0 V 5 pF ns Unit
Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels
VIO = 1.8 V (PL127J) VIO = 3.0 V
0.0 - 1.8 0.0-3.0 VIO/2 VIO/2
V V V
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Switching Waveforms
Table 22.
Waveform Inputs Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z)
Key to Switching Waveforms
Outputs
VIO 0.0 V
In
VIO/2
Measurement Level
VIO/2
Output
Figure 10.
Input Waveforms and Measurement Levels
VCC RampRate
All DC characteristics are specified for a VCC ramp rate > 1V/100 s and VCC >=VCCQ - 100 mV. If the VCC ramp rate is < 1V/100 s, a hardware reset required.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
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Read Operations
Table 23.
Parameter JEDEC tAVAV tAVQV tELQV Std. tRC tACC tCE Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay CE#, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Max Min Min Min 55 55 55 55 20 20
Read-Only Operations
Speed Options 60 60 60 60 25 25 16 16 5 0 10 65 65 65 65 30 30 70 70 70 70 Unit ns ns ns ns ns ns ns ns ns ns
tPACC Page Access Time tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Output Enable to Output Delay Chip Enable to Output High Z (Note 3) Output Enable to Output High Z (Notes 1, 3) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 3) Output Enable Hold Time (Note 1) Read Toggle and Data# Polling
tOEH
Notes: 1. Not 100% tested. 2. See Figure 9 and Table 21 for test specifications. 3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC /2. The time from OE# high to the data bus driven to VCC /2 is taken as tDF. 4. For 70pF Output Load Capacitance, 2 ns will be added to the above tACC,tCE,tPACC,tOE values for all speed grades.
tRC Addresses CE# tRH tRH OE# tOEH WE# HIGH Z Data RESET# RY/BY# Valid Data tCE tOH HIGH Z tOE tDF Addresses Stable tACC
0V
Figure 11.
Read Operation Timings
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Amax-A3
Same Page
A2-A0
Aa
tACC
Ab
tPACC
Ac
tPACC tPACC
Ad
Data CE# OE#
Figure 12.
Qa
Qb
Qc
Qd
Page Read Operation Timings
Reset
Table 24.
Parameter JEDEC Std tReady tReady tRP tRH tRPD tRB Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode RY/BY# Recovery Time Max Max Min Min Min Min All Speed Options 35 500 500 50 20 0 Unit s ns ns ns s ns
Hardware Reset (RESET#)
Note: Not 100% tested.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
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RY/BY#
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
tReady RY/BY# tRB CE#, OE#
RESET# tRP
Figure 13.
Reset Timings
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Erase/Program Operations
Table 25. Erase and Program Operations
Parameter JEDEC tAVAV tAVWL Std tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH tSR/W tWHWH1 tWHWH1 tWHWH2 tWHWH1 tWHWH1 tWHWH2 tVCS tRB tBUSY Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Latency Between Read and Write Operations Programming Operation (Note 2) Accelerated Programming Operation (Note 2) Sector Erase Operation (Note 2) VCC Setup Time (Note 1) Write Recovery Time from RY/BY# Program/Erase Valid to RY/BY# Delay Min Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Min Min Max 35 20 0 6 4 0.5 50 0 90 25 0 10 0 0 0 40 25 30 0 30 55 55 Speed Options 60 60 0 15 35 65 65 70 70 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s sec s ns ns
Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
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Timing Diagrams
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD tBUSY RY/BY# Status DOUT tRB tWPH tWHWH1 PA PA Read Status Data (last two cycles)
tCH
A0h
VCC tVCS
Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address
Figure 14.
Program Operation Timings
VHH
WP#/ACC
VIL or VIH tVHH tVHH
VIL or VIH
Figure 15.
Accelerated Program Timing Diagram
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Erase Command Sequence (last two cycles)
tWC
Addresses 2AAh
Read Status Data
tAS
SA
555h for chip erase
VA
tAH
VA
CE#
OE# tWP WE#
tCH
tCS
tDS
tWPH
tWHWH2
tDH
Data
55h
30h
10 for Chip Erase
Status
DOUT
tBUSY
RY/BY#
tVCS
VCC
tRB
Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status"
Figure 16.
Chip/Sector Erase Operation Timings
tWC
tRC
Valid RA
tWC
Valid PA
tWC
Valid PA
Addresses
tAS
Valid PA
tAH
tACC
tAS tCPH
tAH
CE#
tCE
tOE
tCP
OE#
tOEH
tGHWL
tWP
WE#
tWPH
tDS
tDH
tDF
tOH
Valid Out
Data
Valid In
Valid In
Valid In
tSR/W
WE# Controlled Write Cycle
Read Cycle
CE# Controlled Write Cycles
Figure 17.
Back-to-back Read/Write Cycle Timings
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
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tRC
Addresses VA
VA
VA
tACC
tCE
CE#
tCH
OE#
tOE
tOEH
WE#
tDF
tOH
DQ7
High Z
Complement
Complement
True
Valid Data
High Z
DQ6-DQ0
Status Data
Status Data
True
Valid Data
tBUSY RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle
Figure 18.
Data# Polling Timings (During Embedded Algorithms)
tAHT
tAS
Addresses
tAHT
tASO
CE#
tOEH
tCEPH
WE#
tOEPH
OE#
tDH
DQ6/DQ2
tOE
Valid Status Valid Status Valid Status
Valid Data
Valid Data
(first read)
RY/BY#
(second read)
(stops toggling)
Notes: 1. VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle
Figure 19. Toggle Bit Timings (During Embedded Algorithms)
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Enter Embedded Erasing WE#
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2
Note:Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE#
or CE# to toggle DQ2 and DQ6.
Figure 20.
DQ2 vs. DQ6
Protect/Unprotect
Table 26.
Parameter JEDEC Std tVIDR tVHH tRSP tRRB Description VID Rise and Fall Time (See Note) VHH Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect RESET# Hold Time from RY/BY# High for Temporary Sector Unprotect Min Min Min Min All Speed Options 500 250 4 4 Unit ns ns s s
Temporary Sector Unprotect
Note: Not 100% tested.
VID
RESET#
VID
VIL or VIH
VIL or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
tRRB
Figure 21.
Temporary Sector Unprotect Timing Diagram
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
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VID VIH
RESET#
SA, A6, A1, A0
Valid* Sector Group Protect/Unprotect
Valid* Verify 40h
Valid*
Data 1 s CE#
60h
60h
Status
Sector Group Protect: 150 s Sector Group Unprotect: 15 ms
WE#
OE#
Notes: 1. For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 22. Sector/Sector Block Protect and Unprotect Timing Diagram
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Controlled Erase Operations
Table 27. Alternate CE# Controlled Erase and Program Operations
Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL tWHWH1 tWHWH1 tWHWH2 Std tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH1 tWHWH2 Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Programming Operation (Note 2) Accelerated Programming Operation (Note 2) Sector Erase Operation (Note 2) Min Min Min Min Min Min Min Min Min Min Typ Typ Typ 35 20 6 4 0.5 30 25 0 0 0 0 40 25 55 55 Speed Options 60 60 0 35 30 65 65 70 70 Unit ns ns ns ns ns ns ns ns ns ns s s sec
Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
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555 for program 2AA for erase
PA for program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
RY/BY#
Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device
Table 28.
Alternate CE# Controlled Write (Erase/Program) Operation Timings
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S29PL127J/S29PL064J/S29PL032J for MCP
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
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Table 29.
Parameter Sector Erase Time
PL127J
Erase And Programming Performance
Typ (Note 1)
0.5 135 71 39 6 4 50.4 25.2 12.6
Max (Note 2)
2 216 113.6 62.4 100 60 200 50.4 25.2
Unit
sec sec sec sec s s sec sec sec
Comments Excludes 00h programming prior to erasure (Note 4) Excludes system level overhead (Note 5)
Chip Erase Time
PL064J PL032J
Word Program Time Accelerated Word Program Time Chip Program Time (Note 3)
PL127J PL064J PL032J
Notes: 1. Typical program and erase times assume the following conditions: 25xC, 3.0 V VCC, 100,000 cycles. Additionally, programming typicals assume checkerboard pattern. All values are subject to change. 2. Under worst case conditions of 90xC, VCC = 2.7 V, 100,000 cycles. All values are subject to change. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 17 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
BGA Pin Capacitance
Parameter Symbol CIN COUT CIN2 CIN3 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance WP#/ACC Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Typ 6.3 7.0 5.5 11 Max 7 8 8 12 Unit pF pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
August 12, 2004 S29PL127J_064J_032J_MCP_00_A3
S29PL127J/S29PL064J/S29PL032J for MCP
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Type 2 pSRAM
16Mb (1Mb Word x 16-bit) 32Mb (2Mb Word x 16-bit) 64Mb (4Mb Word x 16-bit) Features
Process Technology: CMOS Organization: x16 bit Power Supply Voltage: 2.7~3.1V Three State Outputs Compatible with Low Power SRAM
Product Information
Density 16Mb 16Mb 32Mb 32Mb 64Mb 64Mb VCC Range 2.7-3.1V 2.7-3.1V 2.7-3.1V 2.7-3.1V 2.7-3.1V 2.7-3.1V Standby (ISB1, Max.) 80 A 80 A 100 A 100 A TBD TBD Operating (ICC2, Max.) 30 mA 35 mA 35 mA 40 mA TBD TBD Mode Dual CS Dual CS and Page Mode Dual CS Dual CS and Page Mode Dual CS Dual CS and Page Mode
Pin Description
Pin Name CS1#, CS2 OE# WE# LB#, UB# A0-A19 (16M) A0-A20 (32M) A0-A21 (64M) I/O0-I/O15 VCC/VCCQ VSS/VSSQ NC DNU Chip Select Output Enable Write Enable Lower/Upper Byte Enable Address Inputs Data Inputs/Outputs Power Supply Ground Not Connection Do Not Use Description I/O I I I I I I/O -- -- -- --
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Type 2 pSRAM
pSRAM_Type02_15A0 May 3, 2004
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Power Up Sequence
1. 2. Apply power. Maintain stable power (VCC min.=2.7V) for a minimum 200 s with CS1#=high or CS2=low.
Timing Diagrams
Power Up
VCC(Min)
VCC Min. 200 s
CS1#
CS2
Power Up Mode Normal Operation
Figure 23.
Notes:
Power Up 1 (CS1# Controlled)
1. After VCC reaches VCC(Min.), wait 200 s with CS1# high. Then the device gets into the normal operation.
VCC(Min) VCC
Min. 200 s
CS1#
CS2 Power Up Mode Normal Operation
Figure 24.
Notes:
Power Up 2 (CS2 Controlled)
1. After VCC reaches VCC(Min.), wait 200 s with CS2 low. Then the device gets into the normal operation.
May 3, 2004 pSRAM_Type02_15A0
Type 2 pSRAM
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Functional Description
Mode Deselected Deselected Deselected Output Disabled Outputs Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write CS1# H X X L L L L L L L L CS2 X L X H H H H H H H H OE# X X X H H L L L X X X WE# X X X H H H H H L L L LB# X X H L X L H L L H L UB# X X H X L H L L H L L I/O1-8 High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN I/O9-16 High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN Power Standby Standby Standby Active Active Active Active Active Active Active Active
Legend:X = Don't care (must be low or high state).
Absolute Maximum Ratings
Item Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Power Dissipation Operating Temperature
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" section may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability.
Symbol VIN , VOUT VCC PD TA
Ratings -0.2 to VCC+0.3V -0.2 to 3.6V 1.0 -40 to 85
Unit V V W C
DC Recommended Operating Conditions
Symbol VCC VSS VIH VIL
Notes:
1. TA=-40 to 85C, otherwise specified. 2. Overshoot: VCC+1.0V in case of pulse width 20ns. 3. Undershoot: -1.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested.
Parameter Power Supply Voltage Ground Input High Voltage Input Low Voltage
Min 2.7 0 2.2 -0.2 (Note 3)
Typ 2.9 0 -- --
Max 3.1 0 VCC + 0.3 (Note 2) 0.6
Unit
V
100
Type 2 pSRAM
pSRAM_Type02_15A0 May 3, 2004
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Capacitance (Ta = 25C, f = 1 MHz)
Symbol CIN COIO Parameter Input Capacitance Input/Output Capacitance Test Condition VIN = 0V VOUT = 0V Min -- -- Max 8 10 Unit pF pF
Note: This parameter is sampled periodically and is not 100% tested.
DC and Operating Characteristics
Common
Item Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Symbol ILI ILO VOL VOH Test Conditions VIN=VSS to VCC CS1#=VIH or CS2=VIL or OE#=VIH or WE#=VIL or LB#=UB#=VIH, VIO=VSS to VCC IOL=2.1mA IOH=-1.0mA Min -1 -1 -- 2.4 Typ -- -- -- -- Max 1 1 0.4 -- Unit A A V V
May 3, 2004 pSRAM_Type02_15A0
Type 2 pSRAM
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16M pSRAM
Item Symbol ICC1 Average Operating Current ICC2 Page Test Conditions Cycle time=1s, 100% duty, IIO=0mA, CS1#0.2V, LB#0.2V and/or UB#0.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN=VIH or VIL Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL Other inputs=0-VCC 1. CS1# VCC - 0.2, CS2 VCC - 0.2V (CS1# controlled) or 2. 0V CS2 0.2V (CS2 controlled)
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from the time when standby mode is set up.
Min Typ Max Unit -- -- 7 mA
Async
--
--
30
mA
35
mA
Standby Current (CMOS)
ISB1 (Note 1)
--
--
80
mA
32M pSRAM
Item Symbol ICC1 Average Operating Current ICC2 Page Test Conditions Cycle time=1s, 100% duty, IIO=0mA, CS1#0.2V, LB#0.2V and/or UB#0.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN=VIH or VIL Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL Other inputs=0-VCC 1. CS1# VCC - 0.2, CS2 VCC - 0.2V (CS1# controlled) or 2. 0V CS2 0.2V (CS2 controlled)
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from the time when standby mode is set up.
Min Typ Max Unit -- -- 7 mA
Async
--
--
35
mA
40
mA
Standby Current (CMOS)
ISB1 (Note 1)
--
--
100 mA
102
Type 2 pSRAM
pSRAM_Type02_15A0 May 3, 2004
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Information
64M pSRAM
Item Symbol ICC1 Average Operating Current ICC2 Page Test Conditions Cycle time=1s, 100% duty, IIO=0mA, CS1#0.2V, LB#0.2V and/or UB#0.2V, CS2VCC-0.2V, VIN0.2V or VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN=VIH or VIL Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS1#=VIL, CS2=VIH LB#=VIL and/or UB#=VIL, VIN-VIH or VIL Other inputs=0-VCC 1. CS1# VCC - 0.2, CS2 VCC - 0.2V (CS1# controlled) or 2. 0V CS2 0.2V (CS2 controlled)
Notes:
1. Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms from the time when standby mode is set up.
Min Typ Max Unit -- -- TBD mA
Async
--
--
TBD
mA
TBD
mA
Standby Current (CMOS)
ISB1 (Note 1)
--
--
TBD
mA
AC Operating Conditions
Test Conditions (Test Load and Test Input/Output Reference)
Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See Figure 25): CL=50pF
Dout
CL
Figure 25.
Note: Including scope and jig capacitance.
Output Load
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Type 2 pSRAM
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ACC Characteristics (Ta = -40C to 85C, VCC = 2.7 to 3.1 V)
Speed Bins 70ns Symbol tRC tAA tCO tOE tBA tLZ Read tBLZ tOLZ tHZ tBHZ tOHZ tOH tPC tPA tWC tCW tAS tAW Write tBW tWP tWR tWHZ tDW tDH tOW
Notes:
1. tWP (min)=70ns for continuous write operation over 50 times.
Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output UB#, LB# Access Time Chip Select to Low-Z Output UB#, LB# Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB#, LB# Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Page Cycle Time Page Access Time Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write UB#, LB# Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z
Min 70 -- -- -- -- 10 10 5 0 0 0 5 25 -- 70 60 0 60 60 55 (Note 1) 0 0 30 0 5
Max -- 70 70 35 70 -- -- -- 25 25 25 -- -- 20 -- -- -- -- -- -- -- 25 -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Timing Diagrams
Read Timings
tRC Address tOH Data Out Previous Data Valid tAA Data Valid
Figure 26.
Notes:
Timing Waveform of Read Cycle(1)
1. Address Controlled, CS1#=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL.
tRC Address tAA tOH
CS1#
tCO
CS2
tHZ UB#, LB# tBA tBHZ OE# tOLZ tBLZ tLZ tOE tOHZ Data Valid
Data out
High-Z
Figure 27.
Notes:
1. WE#=VIH.
Timing Waveform of Read Cycle(2)
Address1)
Valid Address
A1~A0
Valid Address
Valid Address
Valid Address
Valid Address
tAA
tPC
CS1#
CS2
tCO
OE#
tOE DQ15~DQ0 High Z tPA
Data Valid Data Valid Data Valid Data Valid
tOHZ
Figure 28.
Notes:
Timing Waveform of Read Cycle(2)
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Type 2 pSRAM
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1. 16Mb: A2 ~ A19, 32Mb: A2 ~ A20, 64Mb: A2 ~ A21.
tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. tOE(max) is met only when OE# becomes enabled after tAA(max). If invalid address signals shorter than min. tRC are continuously repeated for over 4s, the device needs a normal read timing (tRC) or needs to sustain standby state for min. tRC at least once in every 4s.
Write Timings
tWC Address tCW tWR
CS1#
CS2
tAW tBW tWP WE# tAS Data in High-Z tWHZ Data out Data Undefined tDW Data Valid tOW tDH High-Z
UB#, LB#
Figure 29.
Write Cycle #1 (WE# Controlled)
tWC Address tAS tCW tWR
CS1#
tAW
CS2
tBW tWP
UB#, LB#
WE#
tDW Data in Data Valid tDH
Data out
High-Z
Figure 30.
Write Cycle #2 (CS1# Controlled)
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tWC Address tAS tCW tWR
CS1#
tAW
CS2
tBW tWP(1) WE# tDW Data in Data Valid tDH
UB#, LB#
Data out
High-Z
Figure 31. Timing Waveform of Write Cycle(3) (CS2 Controlled)
tWC Address tCW tWR
CS1#
tAW
CS2
UB#, LB# tAS WE# tDW Data in Data Valid tDH tBW tWP
Data out
High-Z
Figure 32. Timing Waveform of Write Cycle(4) (UB#, LB# Controlled)
Notes:
1. A write occurs during the overlap(tWP) of low CS1# and low WE#. A write begins when CS1# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1# going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS1# or WE# going high.
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Type 2 pSRAM
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pSRAM Type 3
16 Megabit (1M x 16) CMOS Pseudo SRAM Features
Organized as 1M words by 16 bits Fast Cycle Time: 70 ns Standby Current: 100 A Deep power-down Current: 10 A (Memory cell data invalid) Byte data control: LB# (DQ0 - 7), UB# (DQ8 - 15) Compatible with low-power SRAM Single Power Supply Voltage: 3.0V0.3V
Description
pSRAM Type 3 currently includes only a 16M bit device, organized as 1M words by 16 bits. It is designed with advanced CMOS technology specified RAM featuring low-power static RAM-compatible function and pin configuration. This device operates from a single power supply. Advanced circuit technology provides both high speed and low power. It is automatically placed in low-power mode when CS1# or both UB# and LB# are asserted high or CS2 is asserted low. There are three control inputs. CS1# and CS2 are used to select the device, and output enable (OE#) provides fast memory access. Data byte control pins (LB#,UB#) provide lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required.
Pin Description
A0 - A19 DQ0 - DQ15 CE1# CE2 OE# WE# LB# UB# VCC VSS = = = = = = = = = = Address Inputs Data Inputs/Outputs Chip Enable Deep Power Down Output Enable Write Control Lower Byte Control Upper Byte Control Power Supply Ground
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Operation Mode
MODE Deselect Deselect Deselect Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write CE1# H X L L L L L L L L L CE2 H L H H H H H H H H H OE# X X X H H L L L X X X WE# X X X H H H H H L L L LB# X X H L X L H L L H L UB# X X H X L H L L H L L DQ0 to DQ7 High-Z High-Z High-Z High-Z High-Z D-out High-Z D-out D-in High-Z D-in DQ8 to DQ15 High-Z High-Z High-Z High-Z High-Z High-Z D-out D-out High-Z D-in D-in POWER Standby Deep Power Down Standby Active Active Active Active Active Active Active Active
Note: X = don't care. H = logic high. L = logic low.
Absolute Maximum Ratings (see Note)
SYMBOL VCC VIN VIN, VOUT ISH PD RATING Supply Voltage Input Voltages Output and output Voltages Output short circuit current Power Dissipation VALUE -0.2 to +3.6 -0.2 to VCC + 0.3 -2.0 to +3.6 100 1 UNIT V V V mA W
Note: Absolute maximum DC requirements contains stress ratings only. Functional operation at the absolute maximum limits is not implied or guaranteed. Extended exposure to maximum ratings may affect device reliability.
DC Characteristics
Table 30.
SYMBOL VDD VSS VIH VIL PARAMETER Power Supply Voltage Ground Input High Voltage Input Low Voltage
DC Recommended Operating Conditions
MIN 2.7 0 2.2 -0.2 (Note 2) TYP. 3.0 MAX 3.3 0 VCC + 0.2 (Note 1) +0.6 V UNIT
Notes: 1. Overshoot: VCC + 2.0V in case of pulse width 20ns 2. Undershoot: -2.0V in case of pulse width 20ns 3. Overshoot and undershoot are sampled, not 100% tested.
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Table 31.
SYMBOL IIL ILO
DC Characteristics (TA = -25C to 85C, VDD = 2.6 to 3.3V)
TEST CONDITION VIN = VSS to VDD VIO = VSS to VDD CE1# = VIH, CE2 = VIL or OE# = VIH or WE# = VIL Cycle time = Min., 100% duty, IIO = 0mA, CE1# = VIL, CE2 = VIH, VIN = VIH or VIL Cycle time = 1s, 100% duty IIO = 0mA, CE1# 0.2V, CE2 VDD -0.2V, VIN 0.2V or VIN VDD -0.2V CE1# = VDD - 0.2V and CE2 = VDD - 0.2V, Other inputs = VSS ~ VCC CE2 0.2V, Other inputs = VSS ~ VCC IOL = 2.1mA IOH = -1.0mA 2.4 MIN -1 -1 MAX UNIT 1 1 A A
PARAMETER Input Leakage Current Output Leakage Current
ICC1
Operating Current @ Min. Cycle Time
-
35
mA
ICC2
Operating Current @ Max Cycle Time
-
5
mA
ISB1 ISBD VOL VOH
Standby Current (CMOS) Deep Power-down Output Low Voltage Output High Voltage
-
100 10 0.4 -
A A V V
AC Characteristics
Table 32. AC Characteristics and Operating Conditions (TA = -25C to 85C, VDD = 2.6 to 3.3V)
70 Cycle Symbol tRC tAA tCO1 tCO2 tOE tBA Read tLZ tOLZ tBLZ tHZ tOHZ tBHZ tOH Parameter Read Cycle Time Address Access Time Chip Enable (CE#1) Access Time Chip Enable (CE2) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output in Low-Z Output Enable Low to Output in Low-Z Data Byte Control Low to Output in Low-Z Chip Enable High to Output in High-Z Output Enable High to Output in High-Z Data Byte Control High to Output in High-Z Output Data Hold Time Min 70 10 5 10 10 Max 70 70 70 35 70 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
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Table 32.
AC Characteristics and Operating Conditions (TA = -25C to 85C, VDD = 2.6 to 3.3V) (Continued)
70
Cycle
Symbol tWC tWP tAW tCW tBW
Parameter Write Cycle Time Write Pulse Width Address Valid to End of Write Chip Enable to End of Write Data Byte Control to End of Write Address Set-up Time Write Recovery Time WE# Low to Output High-Z WE# High to Output in High-Z Data to Write Overlap Data Hold Time WE# High Time
Min 70 50 60 60 60 0 0 5 35 0 5
Max 20 10
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Write
tAS tWR tWZH tOW tDW tDH tWEH
Table 33. AC Test Conditions
Parameter Output load Input pulse level Timing measurements
tR, tF
Condition 50 pF + 1 TTL Gate 0.4 V, 2.4 0.5 x VCC 5 ns
R L = 50 D OUT Z0 = 50 V L = 1.5 V C L = 50 pF (see Note)
Note: Including scope and jig capacitance
Figure 33.
AC Test Loads
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pSRAM Type 3
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Deep Pow er Down Exit Sequence
Deep Powe r Down Mode
CE2=VIH
Powe r on
Initial State (Wait 200 s)
Activee
CE2=VIL CE2=VIH, CE1# =VIH or UB#, LB# =VIH
CE2=VIL
Powe r Up Sequence
CE1# =VIL, CE2=VIH, UB# & LB# or/and LB# = VIL
Standby Mode
Figure 34. Table 34.
Power Mode Standby Deep Power Down
State Diagram
Standby Mode Characteristics
Standby Current (A) 100 10 Wait Time (s) 0 200
Memory Cell Data Valid Invalid
Timing Diagrams
tRC Address tA A tOH Data Out Previous Data Valid
tOH Data Valid
Note: CE1# = OE# = VIL, CE2 = WE# = VIH, UB# and/or LB# = VIL
Figure 35.
Read Cycle 1--Addressed Controlled
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Deep Power Down Entry Sequence
CE1# = VIH or VIL, CE2=VIH
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tRC
Address tA A tLZ tCO
tOH
CE1#
UB#, LB#
tBLZ
tBA
tHZ
tOE OE#
tBHZ
Data Out
High-Z
tOLZ
tOHZ Data Valid High-Z
Note: CE2 = WE# = VIH
Figure 36.
Read Cycle 2--CS1# Controlled
tWC Address tAW tCW tWR
CE1#
UB#, LB#
tBW
WE# tAS High-Z tWHZ Data Out Data Undefined
tWP tDW Data Valid tDH High-Z
Data In
tOW
Notes: 1. CE2 = VIH 2. CE2 = WE# = VIH
Figure 37.
Write Cycle 1--WE# Controlled
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tWC Address tAW tCW tWR
tAS CE1#
UB#, LB#
tBW
WE#
tWP tDW tDH
Data In
Data Valid
Notes: 1. CE2 = VIH
Data Out
High-Z
2. CE2 = WE# = VIH
Figure 38.
Write Cycle 2--CS1# Controlled
tWC Address tAW tCW tWR
CE1#
UB#, LB#
tAS
tBW
WE#
tWP tDW tDH
Data In
Data Valid
Notes: 1. CE2 = VIH
Data Out
High-Z
2. CE2 = WE# = VIH
Figure 39.
Write Cycle3--UB#, LB# Controlled
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200 s ~ ~ CE2 1 s
Normal Operation Mode
Suspend
Deep Power Down Mode
Wake Up Normal Operation ~ ~
CE1#
Figure 40.
Deep Power-down Mode
200 s
~ ~
VCC
CE2
CE1#
Figure 41.
Power-up Mode
> 15s CE1#
WE#
< tRC
Address
Note: The S71JL064HA0 Model 61 has a timing that is not supported at read operation. Data will be lost if your system has multiple invalid address signal shorter than tRC during over 15s at the read operation shown above.
Figure 42. Abnormal Timing
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pSRAM Type 4
4 Mbit (256K x 16) Features
Wide voltage range: 2.7V to 3.3V Typical active current: 3 mA @ f = 1 MHz Low standby power Automatic power-down when deselected
Functional Description
The Type 4 pSRAM is a high-performance CMOS pseudo static RAM (pSRAM) organized as 256K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. The device can be put into standby mode reducing power consumption dramatically when deselected (CE1# Low, CE2 High or both BHE# and BLE# are High). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1# High, CE2 Low, OE# is deasserted High), or during a write operation (Chip Enabled and Write Enable WE# Low). Reading from the device is accomplished by asserting the Chip Enables (CE1# Low and CE2 High) and Output Enable (OE#) Low while forcing the Write Enable (WE#) High. If Byte Low Enable (BLE#) is Low, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE#) is Low, then data from memory will appear on I/O8 to I/O15. See Table 37 for a complete description of read and write modes.
Product Portfolio
Power Dissipation Operating, ICC (mA) VCC Range (V) Min 2.7V Typ 3.0V Max 3.3V Speed (ns) 70 ns f = 1 MHz Typ. (note 1) 3 Max 5 f = fmax Typ. (note 1) TBD Max 25 mA Standby (ISB2) (A) Typ. (note 1) 15 Max 40
Notes: 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ) and TA = 25C.
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . -40C to +85C Supply Voltage to Ground Potential . . . . . . . . . . . . . . . . . . . . . -0.4V to 4.6V DC Voltage Applied to Outputs in High-Z State (note 1, 2, 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 3.7V DC Input Voltage (note 1, 2, 3) . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 3.7V Output Current into Outputs (Low). . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Static Discharge Voltage . . . . . . . . . >2001V (per MIL-STD-883, Method 3015) Latch-up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA
Notes: 1. VIH(MAX) = VCC + 0.5V for pulse durations less than 20 ns. 2. VIL(MIN) = -0.5V for pulse durations less than 20 ns. 3. Overshoot and undershoot specifications are characterized and are not 100% tested.
Operating Range
Ambient Temperature (TA) -25C to +85C VCC 2.7V to 3.3V
Table 35. DC Electrical Characteristics (Over the Operating Range)
Parameter VCC VOH VOL VIH VIL IIX IOZ ICC Description Supply Voltage Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current F=0 GND VIN VCC GND VOUT VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = 3.3V IOUT = 0 mA CMOS Levels IOH = -1.0 mA IOL = 0.1 mA 0.8 * VCC -0.4 -1 -1 TBD Test Conditions Min. 2.7 VCC - 0.4 0.4 VCC + 0.4 0.4 +1 +1 15 3 A V Typ. (note 1) Max 3.3 Unit
mA
ISB1
Automatic CE# Power-Down Current--CMOS Inputs
CE# VCC - 0.2V, CE2 0.2V VIN VCC - 0.2V, VIN 0.2V, f = fmax (Address and Data Only), f=0 (OE#, WE#, BHE# and BLE#) CE# VCC - 0.2V, CE2 0.2V VIN VCC - 0.2V or VIN 0.2V, f = 0, VCC = 3.3V
250 A 40
ISB2
Automatic CE# Power-Down Current--CMOS Inputs
Notes: 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
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Capacitance
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Condition TA = 25C, f = 1 MHz, VCC = VCC(typ.) Max 8 8 Unit pF
Note: Tested initially and after any design or process changes that may affect these parameters.
Thermal Resistance
Parameter JA JC Description Test Conditions VFBGA 55 17 C/W Unit Thermal Resistance (Junction to Ambient) Test conditions follow standard test methods and procedures for measuring thermal Thermal Resistance (Junction to Case) impedance, per EIA / JESD51.
Note: Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 R1
ALL INPUT PULSES VCC GND Rise Time: 1 V/ns 10% 90% 90% 10% Fall Time: 1 V/ns
Equivalent to:
THE VENIN EQUIVALENT RTH VTH
OUTPUT
Figure 43.
Parameters R1 R2 RTH VTH
AC Test Loads and Waveforms
3.0V VCC 22000 22000 11000 1.50 V Unit
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Table 36.
Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tDBE tLZBE tHZBE tSK (note 4) Read Cycle Time Address to Data Valid
Switching Characteristics
Description Min Max Unit
70 70 10 70 35 5 25 5 25 70 5 25 10 ns
Data Hold from Address Change CE#1 Low and CE2 High to Data Valid OE# Low to Data Valid OE# Low to Low Z (note 2, 3) OE# High to High Z (note 2, 3) CE#1 Low and CE2 High to Low Z (note 2, 3) CE#1 High and CE2 Low to High Z (note 2, 3) BHE# / BLE# Low to Data Valid BHE# / BLE# Low to Low Z (note 2, 3) BHE# / BLE# High to High Z (note 2, 3) Address Skew
Write Cycle (note 5) tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Write Cycle Time CE#1 Low an CE2 High to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE# Pulse Width BLE# / BHE# LOW to Write End Data Set-up to Write End Data Hold from Write End WE# Low to High Z (note 2, 3) WE# High to Low Z (note 2, 3) 5 70 55 55 0 0 55 55 25 0 25 ns
Notes: 1. Test conditions assume signal transition time of 1V/ns or higher, timing reference levels of VCC(typ.) /2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 2. tHZOE, tHZCE, tHZBE and tHZWE transitions are measured when the outputs enter a high-impedance state. 3. High-Z and Low-Z parameters are characterized and are not 100% tested. 4. To achieve 55-ns performance, the read access should be CE# controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. 5. The internal write time of the memory is defined by the overlap of WE#, CE#1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input setup and hold timing should be referenced to the edge of the signal that terminates write.
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Switching Waveforms
tRC ADDRESS tSK DATA OUT tOHA tAA DATA VALID
PREVIOUS D ATA VALID
Figure 44.
Read Cycle 1 (Address Transition Controlled)
Notes: 1. To achieve 55-ns performance, the read access should be CE# controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. 2. Device is continuously selected. OE#, CE# = VIL. 3. WE# is High for Read Cycle.
ADDRESS
CE#1
tSK
tRC
CE2
tACE
tHZCE
BHE#/BLE#
tLZBE
OE#
tDBE
tHZBE tHZOE HIGH IMPEDENCE
DATA OUT
tLZOE HIGH IMPEDENCE tLZCE
tDOE DATA VALID
Figure 45.
Read Cycle 2 (OE# Controlled)
Notes: 1. To achieve 55-ns performance, the read access should be CE# controlled. In this case tACE is the critical parameter and tSK is satisfied when the addresses are stable prior to chip enable going active. For the 70-ns cycle, the addresses must be stable within 10 ns after the start of the read cycle. 2. WE# is High for Read Cycle.
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Figure 46.
Write Cycle 1 (WE# Controlled)
Notes: 1. High-Z and Low-Z parameters are characterized and are not 100% tested. 2. The internal write time of the memory is defined by the overlap of WE#, CE#1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input setup and hold timing should be referenced to the edge of the signal that terminates write. 3. Data I/O is high impedance if OE# VIH. 4. If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state. 5. During the Don't Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.
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tWC ADDRESS tSCE CE#1 CE2 tSA WE# BHE#/BLE# tBW tAW tPWE tHA
OE# tSD DATA I/O
DON'T CARE
tHD
VALID DATA tHZOE
Figure 47. Write Cycle 2 (CE#1 or CE2 Controlled)
Notes: 1. High-Z and Low-Z parameters are characterized and are not 100% tested. 2. The internal write time of the memory is defined by the overlap of WE#, CE#1 = VIL, CE2 = VIH, BHE and/or BLE =VIL. All signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input setup and hold timing should be referenced to the edge of the signal that terminates write. 3. Data I/O is high impedance if OE# VIH. 4. If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state. 5. During the Don't Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.
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tWC ADDRESS tSCE CE#1 CE2
BHE#/BLE#
tBW tAW tHA
tSA WE#
tPWE
tSD DATA I/O DON'T CARE tHZWE VALID DATA
tHD
tLZWE
Figure 48.
Write Cycle 3 (WE# Controlled, OE# Low)
Notes: 1. If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state. 2. During the Don't Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.
CE#1 CE2
BHE#/BLE#
WE#
Figure 49.
Write Cycle 4 (BHE#/BLE# Controlled, OE# Low)
Notes: 1. If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state. 2. During the Don't Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.
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Truth Table
Table 37.
CE#1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE# X X X H H H H H H L L L OE# X X X L L L H H H X X X BHE# X X H L H L L H L L H L BLE# X X H L L H L L H L L H Inputs / Outputs High-Z High-Z High-Z Data Out (I/O0-I/O15) Data Out (I/O0 -I/O7); I/O8-I/O15 in High Z Data Out (I/O8-I/O15); I/O0-I/O7 in High Z High-Z High-Z High-Z Data In (I/O0-I/O15) Data In (I/O0-I/O7); I/O8-I/O15 in High Z Data In (I/O8-I/O15); I/O0 -I/O7 in High Z Read (Upper Byte and Lower Byte) Read (Upper Byte only) Read (Lower Byte only) Output Disabled Output Disabled Output Disabled Write (Upper Byte and Lower Byte) Write (Lower Byte Only) Write (Upper Byte Only) Active (ICC) Deselect/Power-Down Standby (ISB)
Truth Table
Mode Power
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pSRAM Type 6
2M Word by 16-bit Cmos Pseudo Static RAM (32M Density) 4M Word by 16-bit Cmos Pseudo Static RAM (64M Density) Features
Single power supply voltage of 2.6 to 3.3 V Direct TTL compatibility for all inputs and outputs Deep power-down mode: Memory cell data invalid Page operation mode: -- Page read operation by 8 words Logic compatible with SRAM R/W () pin Standby current -- Standby = 70 A (32M) -- Standby = 100 A (64M) -- Deep power-down Standby = 5 A Access Times 32M 64M Access Time CE1# Access Time OE# Access Time Page Access Time 70 ns 70 ns 25 ns 30 ns
Pin Description
Pin Name A0 to A21 A0 to A2 I/O1 to I/O16 CE1# CE2 WE# OE# LB#,UB# VDD GND NC Address Inputs Page Address Inputs Data Inputs/Outputs Chip Enable Input Chip select Input Write Enable Input Output Enable Input Data Byte Control Inputs Power Supply Ground Not Connection Description
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pSRAM Type 6
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Functional Description
Mode Read (Word) Read (Lower Byte) Read (Upper Byte) Write (Word) Write (Lower Byte) Write (Upper Byte) Outputs Disabled Standby Deep Power-down Standby CE1# L L L L L L L H H CE2 H H H H H H H H L OE# L L L X X X H X X WE# H H H L L L H X X LB# L L H L L H X X X UB# L H L L H L X X X Address X X X X X X X X X I/O1-8 DOUT DOUT High-Z DIN DIN Invalid High-Z High-Z High-Z I/O9-16 DOUT High-Z DOUT DIN Invalid DIN High-Z High-Z High-Z Power IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDO IDDSD
Legend:L = Low-level Input (VIL), H = High-level Input (VIH), X = VIL or VIH, High-Z = High Impedance.
Absolute Maximum Ratings
Symbol VDD VIN VOUT Topr Tstrg PD IOUT Rating Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current Value -1.0 to 3.6 -1.0 to 3.6 -1.0 to 3.6 -40 to 85 -55 to 150 0.6 50 Unit V V V C C W mA
DC Recommended Operating Conditions (Ta = -40C to 85C)
Symbol VDD VIH VIL Parameter Power Supply Voltage Input High Voltage Input Low Voltage Min 2.6 2.0 -0.3 (Note) Typ 2.75 -- -- Max 3.3 VDD + 0.3 (Note) 0.4 V Unit
Note: VIH (Max) VDD = 1.0 V with 10 ns pulse width. VIL (Min) -1.0 V with 10 ns pulse width.
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pSRAM Type 6
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DC Characteristics (Ta = -40C to 85C, VDD = 2.6 to 3.3 V) (See Note 3 to 4)
Symbol IIL ILO VOH VOL IDDO1 IDDO2 IDDS IDDSD Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Operating Current Page Access Operating Current Standby Current(MOS) Deep Power-down Standby Current VIN = 0 V to VDD Output disable, VOUT = 0 V to VDD IOH = - 0.5 mA IOL = 1.0 mA CE1#= VIL, CE2 = VIH, IOUT = 0 mA, tRC = min ET5UZ8A-43DS ET5VB5A-43DS Test Condition Min -1.0 -1.0 2.0 -- -- -- -- -- -- -- Typ. -- -- 3/4 -- -- -- -- -- -- -- Max +1.0 +1.0 V 0.4 40 50 25 70 100 5 Unit A A V V mA mA mA A A
CE1#= VIL, CE2 = VIH, IOUT = 0 mA Page add. cycling, tRC = min CE1# = VDD - 0.2 V, CE2 = VDD - 0.2 V CE2 = 0.2 V ET5UZ8A-43DS ET5VB5A-43DS
Capacitance (Ta = 25C, f = 1 MHz)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = GND VOUT = GND Max 10 10 Unit pF pF
Note: This parameter is sampled periodically and is not 100% tested.
AC Characteristics and Operating Conditions
(Ta = -40C to 85C, VDD = 2.6 to 3.3 V) (See Note 5 to 11)
Symbol tRC tACC tCO tOE tBA tCOE tOEE tBE tOD tODO tBD Read Cycle Time Address Access Time Chip Enable (CE1#) Access Time Output Enable Access Time Data Byte Control Access Time Chip Enable Low to Output Active Output Enable Low to Output Active Data Byte Control Low to Output Active Chip Enable High to Output High-Z Output Enable High to Output High-Z Data Byte Control High to Output High-Z Parameter Min 70 -- -- -- -- 10 0 0 -- -- -- Max 10000 70 70 25 25 -- -- -- 20 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns
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Symbol tOH tPM tPC tAA tAOH tWC tWP tCW tBW tAW tAS tWR tCEH tWEH tODW tOEW tDS tDH tCS tCH tDPD tCHC tCHP Output Data Hold Time Page Mode Time Page Mode Cycle Time
Parameter
Min 10 70 30 -- 10 70 50 70 60 60 0 0 10 6 -- 0 30 0 0 300 10 0 30
Max -- 10000 -- 30 -- 10000 -- -- -- -- -- -- -- -- 20
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Page Mode Address Access Time Page Mode Output Data Hold Time Write Cycle Time Write Pulse Width Chip Enable to End of Write Data Byte Control to End of Write Address Valid to End of Write Address Set-up Time Write Recovery Time Chip Enable High Pulse Width Write Enable High Pulse Width WE# Low to Output High-Z WE# High to Output Active Data Set-up Time Data Hold Time CE2 Set-up Time CE2 Hold Time CE2 Pulse Width CE2 Hold from CE1# CE2 Hold from Power On
-- -- -- -- -- -- --
ns ns ns s ms ns s
AC Test Conditions
Parameter Output load Input pulse level Timing measurements Reference level tR, tF Condition 30 pF + 1 TTL Gate VDD - 0.2 V, 0.2 V VDD x 0.5 VDD x 0.5 5 ns
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pSRAM Type 6
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Timing Diagrams
Read Timings
tRC Address A0 to A20(32M) A0 to A21(64M)
tACC
tCO
tOH
CE1#
CE2 tOE OE# tODO
WE#
Fix-H tOD
tBA UB#, LB# tBE DOUT I/O1 to I/O16 tOEE Hi-Z tCOE INDETERMINATE VALID DATA OUT Hi-Z tBD
Figure 50.
Read Cycle
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tPM Address A0 to A2 Address A3 to A20(32M) A3 to A21(64M)
CE1#
tRC
tPC
tPC
tPC
CE2
Fix-H
OE#
WE#
UB#, LB# tBA DOUT I/O1 to I/O16 tOE tOEE DOUT tCOE tCO tAA tAOH DOUT tAA tAOH DOUT tAOH tBD tOH DOUT Hi-Z tOD
tBE Hi-Z
tACC
tAA tODO * Maximum 8 words
Figure 51.
Page Read Cycle (8 Words Access)
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pSRAM Type 6
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Write Timings
tWC Address A0 to A20(32M) A0 to A21(64M) tAS
WE#
tAW tWP tWR
tWEH
tCW
CE1#
tWR
tCH CE2 tBW UB#, LB# tODW DOUT I/O1 to I/O16 DIN I/O1 to I/O16 (See Note 9) (See Note 10) Hi-Z tDS tDH (See Note 9) tOEW (See Note 11) tWR
VALID DATA IN
Figure 52.
Write Cycle #1 (WE# Controlled) (See Note 8)
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pSRAM Type 6
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tWC Address A0 to A20(32M) A0 to A21(64M) tAS
WE#
tAW tWP tWR
tCEH tCW
CE1#
tWR
tCH CE2 tBW UB#, LB# tBE DOUT I/O1 to I/O16 Hi-Z tCOE tDS DIN I/O1 to I/O16 (See Note 9) tDH tODW Hi-Z tWR
VALID DATA IN
Figure 53.
Write Cycle #2 (CE# Controlled) (See Note 8)
Deep Power-down Timing
CE1#
tDPD CE2 tCS tCH
Figure 54.
Deep Power Down Timing
Power-on Timing
VDD VDD min
CE1#
tCHC
CE2 tCHP
tCH
Figure 55.
Power-on Timing
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pSRAM Type 6
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Provisions of Address Skew
Read
In case multiple invalid address cycles shorter than tRC min sustain over 10 s in an active status, at least one valid address cycle over tRC min is required during 10s.
over 10s
CE1#
WE#
Address tRCmin
Figure 56. Write
Read
In case multiple invalid address cycles shorter than tWC min sustain over 10 s in an active status, at least one valid address cycle over tWC min is required during 10 s.
CE1#
tWPmin
WE#
Address tWCmin
Figure 57.
Notes:
Write
1. Stresses greater than listed under "Absolute Maximum Ratings" section may cause permanent damage to the device. 2. All voltages are reference to GND. 3. IDDO depends on the cycle time. 4. IDDO depends on output loading. Specified values are defined with the output open condition. 5. AC measurements are assumed tR, tF = 5 ns. 6. Parameters tOD, tODO, tBD and tODW define the time at which the output goes the open condition and are not output voltage reference levels. 7. Data cannot be retained at deep power-down stand-by mode. 8. If OE# is high during the write cycle, the outputs will remain at high impedance. 9. During the output state of I/O signals, input signals of reverse polarity must not be applied. 10. If CE1# or LB#/UB# goes LOW coincident with or after WE# goes LOW, the outputs will remain at high impedance. 11. If CE1# or LB#/UB# goes HIGH coincident with or before WE# goes HIGH, the outputs will remain at high impedance.
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pSRAM Type 6
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pSRAM Type 7
CMOS 1M/2M/4M-Word x 16-bit Fast Cycle Random Access Memory with Low Power SRAM Interface 16Mb (1M word x 16-bit) 32Mb (2M word x 16-bit) 64Mb (4M word x 16-bit) Features
Asynchronous SRAM Interface Fast Access Time -- tCE = tAA = 60ns max (16M) -- tCE = tAA = 65ns max (32M/64M) 8 words Page Access Capability -- tPAA = 20ns max (32M/64M) Low Voltage Operating Condition -- VDD = +2.7V to +3.1V Wide Operating Temperature -- TA = -30C to +85C Byte Control by LB and UB Various Power Down modes -- Sleep (16M) -- Sleep, 4M-bit Partial, or 8M-bit Partial (32M) -- Sleep, 8M-bit Partial, or 16M-bit Partial (64M)
Pin Description
Pin Name A21 to A0 CE1# CE2# WE# OE# UB# LB# DQ16-9 DQ8-1 VDD VSS Description Address Input: A19 to A0 for 16M, A20 to A0 for 32M, A21 to A0 for 64M Chip Enable (Low Active) Chip Enable (High Active) Write Enable (Low Active) Output Enable (Low Active) Upper Byte Control (Low Active) Lower Byte Control (Low Active) Upper Byte Data Input/Output Lower Byte Data Input/Output Power Supply Ground
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pSRAM Type 7
pSRAM_Type07_13_A1 November 2, 2004
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Functional Description
Mode Standby (Deselect) Output Disable (Note 1) Output Disable (No Read) Read (Upper Byte) Read (Lower Byte) Read (Word) No Write Write (Upper Byte) Write (Lower Byte) Write (Word) Power Down L X X X L H H L H L CE2# H CE1# H WE# X H OE# X H LB# X X H H L L H H L L X UB# X X H L H L H L H L X A21-0 X Note 3 Valid Valid Valid Valid Valid Valid Valid Valid X DQ8-1 High-Z High-Z High-Z High-Z Output Valid Output Valid Invalid Invalid Input Valid Input Valid High-Z DQ16-9 High-Z High-Z High-Z Output Valid High-Z Output Valid Invalid Input Valid Invalid Input Valid High-Z
Legend:L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance.
Notes:
1. Should not be kept this logic condition longer than 1 ms. Please contact local Spansion representative for the relaxation of 1ms limitation. 2. Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the selection of the Power-Down Program, 16M has data retention in all modes except Power Down. Refer to Power Down for details. 3. Can be either VIL or VIH but must be valid before Read or Write.
Power Down (for 32M, 64M Only)
Power Down
The Power Down is a low-power idle state controlled by CE2. CE2 Low drives the device in power-down mode and maintains the low-power idle state as long as CE2 is kept Low. CE2 High resumes the device from power-down mode. These devices have three power-down modes. These can be programmed by series of read/write operation. Each mode has following features. 32M Mode Sleep (default) 4M Partial 8M Partial Retention Data No 4M bit 8M bit Retention Address N/A 00000h to 3FFFFh 00000h to 7FFFFh Mode Sleep (default) 8M Partial 16M Partial 64M Retention Data No 8M bit 16M bit Retention Address N/A 00000h to 7FFFFh 00000h to FFFFFh
The default state is Sleep and it is the lowest power consumption but all data is lost once CE2 is brought to Low for Power Down. It is not required to program to Sleep mode after power-up.
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Power Down Program Sequence
The program requires 6 read/write operations with a unique address. Between each read/write operation requires that device be in standby mode. The following table shows the detail sequence. Cycle # 1st 2nd 3rd 4th 5th 6th Operation Read Write Write Write Write Read Address 3FFFFFh (MSB) 3FFFFFh 3FFFFFh 3FFFFFh 3FFFFFh Address Key Data Read Data (RDa) RDa RDa Don't Care (X) X Read Data (RDb)
The first cycle reads from the most significant address (MSB). The second and third cycle are to write back the data (RDa) read by first cycle. If the second or third cycle is written into the different address, the program is cancelled, and the data written by the second or third cycle is valid as a normal write operation. The fourth and fifth cycles write to MSB. The data from the fourth and fifth cycles is "don't care." If the fourth or fifth cycles are written into different address, the program is also cancelled but write data might not be written as normal write operation. The last cycle is to read from specific address key for mode selection. Once this program sequence is performed from a Partial mode to the other Partial mode, the written data stored in memory cell array can be lost. So, it should perform this program prior to regular read/write operation if Partial mode is used.
Address Key
The address key has following format. Mode 32M Sleep (default) 4M Partial 8M Partial N/A 64M Sleep (default) N/A 8M Partial 16M Partial A21 1 1 1 1 A20 1 1 0 0 Address A19 1 0 1 0 A18 - A0 1 1 1 1 Binary 3FFFFFh 37FFFFh 2FFFFFh 27FFFFh
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Absolute Maximum Ratings
Item Voltage of VDD Supply Relative to VSS Voltage at Any Pin Relative to VSS Short Circuit Output Current Storage temperature Symbol VDD VIN, VOUT IOUT TSTG Value -0.5 to +3.6 -0.5 to +3.6 50 -55 to +125 Unit V V mA C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Recommended Operating Conditions (See Warning Below)
Parameter Supply Voltage High Level Input Voltage (Note 1) High Level Input Voltage (Note 1) Ambient Temperature
Notes:
1. Maximum DC voltage on input and I/O pins is VDD+0.2V. During voltage transitions, inputs can positive overshoot to VDD+1.0V for periods of up to 5 ns. 2. Minimum DC voltage on input or I/O pins is -0.3V. During voltage transitions, inputs can negative overshoot VSS to -1.0V for periods of up to 5ns.
Symbol VDD VSS VIH VIL TA
Min 2.7 0 VDD 0.8 -0.3 -30
Max 3.1 0 VDD+0.2 VDD 0.2 85
Unit V V V V C
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges can adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
Package Capacitance
Test conditions: TA = 25C, f = 1.0 MHz Symbol CIN1 CIN2 CIO Description Address Input Capacitance Control Input Capacitance Data Input/Output Capacitance Test Setup VIN = 0V VIN = 0V VIO = 0V Typ -- -- -- Max 5 5 8 Unit pF pF pF
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DC Characteristics (Under Recommended Conditions Unless Otherwise Noted)
16M Parameter Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level Symbol ILI ILO VOH VOL IDDPS VDD Power Down Current IDDP4 IDDP8 IDDP16 IDDS VDD Standby Current IDDS1 IDDA1 IDDA2 VDD = VDD max., VIN = VIH or VIL CE1 = CE2 = VIH VDD = VDD max., VIN 0.2V or VIN VDD - 0.2V, CE1 = CE2 VDD - 0.2V VDD = VDD max., VIN = VIH or VIL, CE1 = VIL and CE2= VIH, IOUT=0mA VDD = VDD max., VIN = VIH or VIL, CE2 0.2 V Test Conditions VIN = VSS to VDD VOUT = VSS to VDD, Output Disable VDD = VDD(min), IOH = -0.5mA IOL = 1mA SLEEP 4M Partial 8M Partial 16M Partial -- Min. Max. 32M Min. Max. 64M Min. Max. Unit A A V V A A A A mA
-1.0 +1.0 -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 -1.0 +1.0 2.2 -- -- 0.4 10 N/A N/A N/A 1 -- 2.4 -- -- -- -- N/A 1.5 -- 0.4 10 40 50 -- -- -- 2.4 -- -- -- 0.4 10 N/A 80 100 1.5
TA< +85C TA< +40C
tRC / tWC = min. tRC / tWC = 1s
170 -- 100 -- 80 -- 90 -- -- 20 3 -- -- 30 3 -- -- 40 5
A A mA mA
VDD Active Current
VDD Page Read Current
Notes:
IDDA3
VDD = VDD max., VIN = VIH or VIL, CE1 = VIL and CE2= VIH, IOUT=0mA, tPRC = min.
N/A
--
10
--
10
mA
1. All voltages are referenced to VSS. 2. DC Characteristics are measured after following POWER-UP timing. 3. IOUT depends on the output load conditions.
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AC Characteristics (Under Recommended Operating Conditions Unless Otherwise Noted)
Read Operation
Parameter Read Cycle Time CE1# Access Time OE# Access Time Address Access Time LB# / UB# Access Time Page Address Access Time Page Read Cycle Time Output Data Hold Time CE1# Low to Output Low-Z OE# Low to Output Low-Z LB# / UB# Low to Output Low-Z CE1# High to Output High-Z OE# High to Output High-Z LB# / UB# High to Output High-Z Address Setup Time to CE1# Low Address Setup Time to OE# Low Address Invalid Time Address Hold Time from CE1# High Address Hold Time from OE# High WE# High to OE# Low Time for Read CE1# High Pulse Width Symbol tRC tCE tOE tAA tBA tPAA tPRC tOH tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASC tASO tAX tCHAH tOHAH tWHOL tCP 5 5 0 0 -- -- -- -6 10 -- -6 -6 10 10 16M Min. 70 -- -- -- -- N/A N/A -- -- -- -- 20 20 20 -- -- 10 -- -- 1000 -- Max. 1000 60 40 60 30 Min. 65 -- -- -- -- -- 20 5 5 0 0 -- -- -- -6 10 -- -6 -6 12 12 32M Max. 1000 65 40 65 30 20 1000 -- -- -- -- 20 14 20 -- -- 10 -- -- -- -- Min. 65 -- -- -- -- -- 20 5 5 0 0 -- -- -- -6 10 -- -6 -6 25 12 64M Max. 1000 65 40 65 30 20 1000 -- -- -- -- 20 14 20 -- -- 10 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 5, 8 9 Notes 1, 2 3 3 3, 5 3 3,6 1, 6, 7 3 4 4 4 3 3 3
Notes:
1. Maximum value is applicable if CE#1 is kept at Low without change of address input of A3 to A21. If needed by system operation, please contact local Spansion representative for the relaxation of 1s limitation. 2. Address should not be changed within minimum tRC. 3. The output load 50 pF with 50 ohm termination to VDD x 0.5 (16M), The output load 50 pF (32M and 64M). 4. 5. 6. 7. The output load 5pF. Applicable to A3 to A21 (32M and 64M) when CE1# is kept at Low. Applicable only to A0, A1 and A2 (32M and 64M) when CE1# is kept at Low for the page address access. In case Page Read Cycle is continued with keeping CE1# stays Low, CE1# must be brought to High within 4 s. In other words, Page Read Cycle must be closed within 4 s. 8. Applicable when at least two of address inputs among applicable are switched from previous state. 9. tRC(min) and tPRC(min) must be satisfied. 10. If actual value of tWHOL is shorter than specified minimum values, the actual tAA of following Read can become longer by the amount of subtracting the actual value from the specified minimum value.
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AC Characteristics
Write Operation
Parameter Write Cycle Time Address Setup Time CE1# Write Pulse Width WE# Write Pulse Width LB#/UB# Write Pulse Width LB#/UB# Byte Mask Setup Time LB#/UB# Byte Mask Hold Time Write Recovery Time CE1# High Pulse Width WE# High Pulse Width LB#/UB# High Pulse Width Data Setup Time Data Hold Time OE# High to CE1# Low Setup Time for Write OE# High to Address Setup Time for Write LB# and UB# Write Pulse Overlap Symbol tWC tAS tCW tWP tBW tBS tBH tWR tCP tWHP tBHP tDS tDH tOHCL tOES tBWO 16M Min. 70 0 45 45 45 -5 -5 0 10 7.5 10 15 0 -5 0 30 Max. 1000 -- -- -- -- -- -- -- -- 1000 1000 -- -- -- -- -- Min. 65 0 40 40 40 -5 -5 0 12 7.5 12 12 0 -5 0 30 32M Max. 1000 -- -- -- -- -- -- -- -- 1000 1000 -- -- -- -- -- Min. 65 0 40 40 40 -5 -5 0 12 7.5 12 12 0 -5 0 30 64M Max. 1000 -- -- -- -- -- -- -- -- 1000 1000 -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 8 9 7 Notes 1,2 3 3 3 3 4 5 6
Notes:
1. Maximum value is applicable if CE1# is kept at Low without any address change. If the relaxation is needed by system operation, please contact local Spansion representative for the relaxation of 1s limitation. 2. Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWR). 3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last. 4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever occurs last. 5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever occurs first. 6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first. 7. tWPH minimum is absolute minimum value for device to detect High level. And it is defined at minimum VIH level. 8. If OE# is Low after minimum tOHCL, read cycle is initiated. In other words, OE# must be brought to High within 5ns after CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met. 9. If OE# is Low after new address input, read cycle is initiated. In other word, OE# must be brought to High at the same time or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met and data bus is in High-Z.
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AC Characteristics
Power Down Parameters
16M Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1# High Hold Time following CE2 High after Power Down Exit [SLEEP mode only] CE1# High Hold Time following CE2 High after Power Down Exit [not in SLEEP mode] CE1# High Setup Time following CE2 High after Power Down Exit
Notes:
1. Applicable also to power-up. 2. Applicable when 4Mb and 8Mb Partial modes are programmed.
32M Min. 10 65 300 1 -- 0 Max. -- -- -- -- --
64M Min. 10 65 300 1 0 Max. -- -- -- -- -- Unit ns ns s s ns 1 2 1 Note
Symbol tCSP tC2LP tCHH tCHHP tCHS
Min. 10 80 300
Max. -- -- --
N/A 0
Other Timing Parameters
16M Parameter CE1# High to OE# Invalid Time for Standby Entry CE1# High to WE# Invalid Time for Standby Entry CE2 Low Hold Time after Power-up CE1# High Hold Time following CE2 High after Power-up Input Transition Time
Notes:
1. Some data might be written into any address location if tCHWX(min) is not satisfied. 2. The Input Transition Time (tT) at AC testing is 5ns as shown in below. If actual tT is longer than 5ns, it can violate the AC specification of some of the timing parameters.
32M Min. 10 10 50 300 1 Max. -- -- -- -- 25
64M Min. 10 10 50 300 1 Max. -- -- -- -- 25 Unit ns ns s s ns 2 1 Note
Symbol tCHOX tCHWX tC2LH tCHH tT
Min. 10 10 50 300 1
Max. -- -- -- -- 25
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AC Characteristics
AC Test Conditions
Symbol VIH VIL VREF tT Input High Level Input Low Level Input Timing Measurement Level Input Transition Time Between VIL and VIH Description Test Setup Value VDD * 0.8 VDD * 0.2 VDD * 0.5 5 Unit V V V ns Note
AC Measurement Output Load Circuits
VDD *0.5 V VDD 0.1 F VSS DEVICE UNDER TEST 50 pF 50 ohm OUT
Figure 58.
AC Output Load Circuit - 16 Mb
VDD 0.1F VSS
DEVICE UNDER TEST 50pF
OUT
Figure 59. AC Output Load Circuit - 32 Mb and 64 Mb
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Timing Diagrams
Read Timings
tRC ADDRESS tASC CE1# tOE OE# tOHZ tBA LB#/UB# tBLZ DQ (Output) tOLZ tCLZ
Note: This timing diagram assumes CE2=H and WE#=H.
ADDRESS VALID tCE tCHAH tCP tCHZ tASC
tBHZ
VALID DATA OUTPUT
tOH
Figure 60.
Read Timing #1 (Basic Timing)
tRC ADDRESS ADDRESS VALID tAA CE1# Low tASO OE# tOE
tAx
tRC ADDRESS VALID tAA tOHAH
LB#/UB# tOLZ DQ (Output) VALID DATA OUTPUT
Note: This timing diagram assumes CE2=H and WE#=H.
tOH
tOH
tOHZ
VALID DATA OUTPUT
Figure 61.
Read Timing #2 (OE# Address Access
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
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tAX ADDRESS tAA CE1#, OE# Low tBA LB#
tRC ADDRESS VALID
tAx
tBA
tBA UB# tBLZ DQ1-8 (Output) DQ9-16 (Output) VALID DATA OUTPUT tBLZ VALID DATA OUTPUT tOH tBHZ tBHZ tOH tBLZ tBHZ tOH
VALID DATA OUTPUT
Note: This timing diagram assumes CE2=H and WE#=H.
Figure 62.
Read Timing #3 (LB#/UB# Byte Access)
tRC ADDRESS (A21-A3) tRC ADDRESS (A2-A0) CE1# OE# LB#/UB# tCLZ DQ (Output) VALID DATA OUTPUT (Normal Access)
Note: This timing diagram assumes CE2=H and WE#=H.
ADDRESS VALID tPRC
ADDRESS VALID
tPRC
ADDRESS VALID
tPRC
ADDRESS VALID
ADDRESS VALID tASC
tPAA
tPAA
tPAA
tCHAH tCHZ
tCE
tOH
tOH
tOH
tOH
VALID DATA OUTPUT (Page Access)
Figure 63.
Read Timing #4 (Page Address Access after CE1# Control Access for 32M and 64M Only)
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tRC ADDRESS (A21-A3) ADDRESS (A2-A0) CE1# Low tASO OE# tBA LB#/UB# DQ (Output) tOLZ tBLZ tOH tOE ADDRESS VALID tRC
ADDRESS VALID
tAX
tRC ADDRESS VALID
tAx
tPRC
ADDRESS VALID
tRC
ADDRESS VALID
tPRC
ADDRESS VALID
tAA
tPAA
tAA
tPAA
tOH
tOH
tOH
VALID DATA OUTPUT (Normal Access)
Notes:
1. This timing diagram assumes CE2=H and WE#=H. 2. Either or both LB# and UB# must be Low when both CE1# and OE# are Low.
VALID DATA OUTPUT (Page Access)
Figure 64.
Read Timing #5 (Random and Page Address Access for 32M and 64M Only)
Write Timings
tWC ADDRESS tAS CE1# tAS WE# tAS LB#, UB# tOHCL OE# DQ (Input) VALID DATA INPUT
Note: This timing diagram assumes CE2=H.
ADDRESS VALID tCW tWR tCP tWP tWR tWHP tBW tWR tBHP tAS tAS tAS
tDS
tDH
Figure 65.
Write Timing #1 (Basic Timing)
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
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tWC ADDRESS tOHAH CE1# Low tAS WE# tWP tWR tWHP tAS ADDRESS VALID
tWC ADDRESS VALID
tWP
tWR
LB#, UB# tOES OE# tOHZ DQ (Input) VALID DATA INPUT
Note:This timing diagram assumes CE2=H.
tDS
tDH
tDS
tDH
VALID DATA INPUT
Figure 66.
Write Timing #2 (WE# Control)
tWC ADDRESS CE1# Low tAS WE# tWR LB# tBS UB# tDS DQ1-8 (Input) VALID DATA INPUT DQ9-16 (Input)
Note: This timing diagram assumes CE2=H and OE#=H.
tWC ADDRESS VALID
ADDRESS VALID
tWP tWHP tBS
tAS
tWP tBH
tBH tDH
tWR
tDS
tDH
Figure 67.
Write Timing #3-1(WE#/LB#/UB# Byte Write Control)
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tWC ADDRESS CE1# Low tWR WE# tAS LB# tBS UB# tDS DQ1-8 (Input) DQ9-16 (Input) tDH tBH tAS tBW tWHP tBS ADDRESS VALID
tWC ADDRESS VALID
tWR
tBH
tBW
VALID DATA INPUT
tDS
tDH
VALID DATA INPUT
Note: This timing diagram assumes CE2=H and OE#=H.
Figure 68.
Write Timing #3-3 (WE#/LB#/UB# Byte Write Control)
tWC ADDRESS CE1# Low ADDRESS VALID
tWC ADDRESS VALID
WE# tAS LB# tBWO DQ1-8 (Input) tAS UB# tDS DQ9-16 (Input) tDH tDS tDH tBW tWR tBHP tDS tDH tAS tBW tWR
VALID DATA INPUT
VALID DATA INPUT
tBW
tWR tBHP
tAS
tBWO tBW tDS
tWR
tDH
VALID DATA INPUT
VALID DATA INPUT
Note: This timing diagram assumes CE2=H and OE#=H.
Figure 69.
Write Timing #3-4 (WE#/LB#/UB# Byte Write Control)
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pSRAM Type 7
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Read/Write Timings
tWC ADDRESS tCHAH CE1# tCP WE# tCP tAS WRITE ADDRESS tCW tWR tASC tRC READ ADDRESS tCE tCHAH
UB#, LB# tOHCL OE# tCHZ tOH
tDS
tDH
tCLZ
tOH
DQ READ DATA OUTPUT
Notes:
1. This timing diagram assumes CE2=H. 2. Write address is valid from either CE1# or WE# of last falling edge.
WRITE DATA INPUT
Figure 70.
Read/Write Timing #1-1 (CE1# Control)
tWC ADDRESS tCHAH CE1# tCP WE# tWP tCP tAS WRITE ADDRESS tWR tASC
tRC READ ADDRESS tCE tCHAH
UB#, LB# tOHCL OE# tCHZ tOH tOE
tDS
tDH
tOLZ
tOH
DQ READ DATA OUTPUT
Notes:
1. This timing diagram assumes CE2=H. 2. OE# can be fixed Low during write operation if it is CE1# controlled write at Read-Write-Read sequence.
WRITE DATA INPUT
READ DATA OUTPUT
Figure 71. 148
Read / Write Timing #1-2 (CE1#/WE#/OE# Control) pSRAM Type 7 pSRAM_Type07_13_A1 November 2, 2004
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tWC ADDRESS tOHAH CE1# Low tAS WE# tOES tWP tWR WRITE ADDRESS
tRC READ ADDRESS tAA tOHAH
UB#, LB# tASO OE# tOHZ tOH tWHOL tDS tDH tOLZ tOE tOHZ tOH
DQ READ DATA OUTPUT
Notes:
1. This timing diagram assumes CE2=H. 2. CE1# can be tied to Low for WE# and OE# controlled operation.
WRITE DATA INPUT
READ DATA OUTPUT
Figure 72.
Read / Write Timing #2 (OE#, WE# Control)
tWC ADDRESS WRITE ADDRESS
tRC READ ADDRESS tAA
CE1#
Low
tOHAH
tOHAH
WE# tOES UB#, LB# tBHZ OE# tOH DQ READ DATA OUTPUT
Notes:
1. This timing diagram assumes CE2=H. 2. CE1# can be tied to Low for WE# and OE# controlled operation.
tAS
tBW
tWR
tBA
tASO tWHOL tDS tDH tBLZ tBHZ tOH
WRITE DATA INPUT
READ DATA OUTPUT
Figure 73.
Read / Write Timing #3 (OE#, WE#, LB#, UB# Control)
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CE1# tCHS tC2LH CE2 tCHH
VDD
0V
VDD min
Note: The tC2LH specifies after VDD reaches specified minimum level.
Figure 74.
Power-up Timing #1
CE1# tCHH CE2
VDD
0V
VDD min
Note: The tCHH specifies after VDD reaches specified minimum level and applicable to both CE1# and CE2.
Figure 75.
Power-up Timing #2
CE1# tCHS CE2 tCSP DQ Power Down Entry tC2LP High-Z Power Down Mode Power Down Exit tCHH (tCHHP)
Note: This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied and Power-Down program was not performed prior to this reset.
Figure 76.
Power Down Entry and Exit Timing
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CE1# tCHOX OE# tCHWX
WE# Active (Read) Standby Active (Write) Standby
Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (min) period for Standby mode from CE1# Low to High transition.
Figure 77.
Standby Entry Timing after Read or Write
tRC ADDRESS MSB*1 tCP CE1#
tWC MSB*1 tCP
tWC MSB*1 tCP
tWC MSB*1 tCP
tWC MSB*1 tCP
tRC Key*2 tCP*3
OE#
WE#
LB#, UB#
DQ*3
RDa Cycle #1
RDa Cycle #2
RDa Cycle #3
X Cycle #4
X Cycle #5
RDb Cycle #6
Notes:
1. The all address inputs must be High from Cycle #1 to #5. 2. The address key must confirm the format specified in page 136. If not, the operation and data are not guaranteed. 3. After tCP following Cycle #6, the Power Down Program is completed and returned to the normal operation.
Figure 78.
Power Down Program Timing (for 32M/64M Only)
November 2, 2004 pSRAM_Type07_13_A1
pSRAM Type 7
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SRAM
4/8 Megabit CMOS SRAM Common Features
Process Technology: Full CMOS Power Supply Voltage: 2.7~3.3V Three state outputs Organization (ISB1, Max.) x8 or x16 (note 1) x8 or x16 (note 1) x8 or x16 (note 1) X16 Standby (ICC2, Max.) 10 A 10 A 15 A TBD
Version F G C D
Notes:
Density 4Mb 4Mb 8Mb 8Mb
Operating 22 mA 22 mA 22 mA TBD
Mode Dual CS, UB# / LB# (tCS) Dual CS, UB# / LB# (tCS) Dual CS, UB# / LB# (tCS) Dual CS, UB# / LB# (tCS)
1. UB#, LB# swapping is available only at x16. x8 or x16 select by BYTE# pin.
Pin Description
Pin Name CS1#, CS2 OE# WE# BYTE# A0~A17 (4M) A0~A18 (8M) SA I/O0~I/O15 VCC VSS DNU NC Chip Selects Output Enable Write Enable Word (VCC)/Byte (VSS) Select Address Inputs Address Input for Byte Mode Data Inputs/Outputs Power Supply Ground Do Not Use No Connection Description I/O I I I I I I I/O -
152
SRAM
SRAM_Type01_02A0 June 15, 2004
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Functional Description
4M Version F, 4M version G, 8M version C
CS1# H X X L L L L L L L L CS2 X L X H H H H H H H H OE# WE# X X X H H L L L X X X X X X H H H H H L L L BYTE# X X X VCC VCC VCC VCC VCC VCC VCC VCC SA X X X X X X X X X X X LB# X X H L X L H L L H L UB# X X H X L H L L H L L IO0~7 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din IO8~15 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Standby Standby Active Active Active Active Active Active Active Active
Note: X means don't care (must be low or high state).
Byte Mode
CS1# H X L L L CS2 X L H H H OE# WE# X X H L X X X H L L BYTE# X X X VCC VCC SA X X X X X LB# X X H L X UB# X X H X L IO0~7 High-Z High-Z High-Z High-Z High-Z IO8~15 High-Z High-Z High-Z High-Z High-Z Mode Deselected Deselected Deselected Output Disabled Output Disabled Power Standby Standby Standby Active Active
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Functional Description
8M Version D
CS1# H X X L L L L L L L L CS2 X L X H H H H H H H H OE# WE# X X X H H L L L X X X X X X H H H H H L L L LB# X X H L X L H L L H L UB# X X H X L H L L H L L IO0~8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din IO9~16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Power Standby Standby Standby Active Active Active Active Active Active Active Active
Note: X means don't care (must be low or high state).
Absolute Maximum Ratings (4M Version F)
Item Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Power Dissipation Operating Temperature Symbol VIN,VOUT VCC PD TA Ratings -0.2 to VCC+0.3V -0.2 to 4.0V 1.0 -40 to 85 Unit V V W C
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Absolute Maximum Ratings (4M Version G, 8M Version C, 8M Version D)
Item Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Power Dissipation Operating Temperature Symbol VIN,VOUT VCC PD TA Ratings -0.2 to VCC+0.3V (Max. 3.6V) -0.2 to 3.6V 1.0 -40 to 85 Unit V V W C
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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DC Characteristics
Recommended DC Operating Conditions (Note 1)
Item Supply voltage Ground Input high voltage Input low voltage Symbol VCC VSS VIH VIL Min 2.7 0 2.2 -0.2 (Note 3) Typ 3.0 0 Max 3.3 0 VCC+0.2 (Note 2) 0.6 Unit V V V V
Notes: 1. TA = -40 to 85C, unless otherwise specified. 2. Overshoot: Vcc+1.0V in case of pulse width 20ns. 3. Undershoot: -1.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested.
Capacitance (f=1MHz, TA=25C)
Item Input capacitance Input/Output capacitance Symbol CIN CIO Test Condition VIN=0V VIO=0V Min Max 8 10 Unit pF pF
Note: Capacitance is sampled, not 100% tested
DC Operating Characteristics
Common
Typ (Note) -
Item Input leakage current Output leakage current Output low voltage Output high voltage
Symbol ILI ILO VOL VOH VIN=VSS to VCC
Test Conditions
Min -1 -1 2.4
Max 1 1 0.4 -
Unit A A V V
CS1#=VIH or CS2=VIL or OE#=VIH or WE#=VIL or LB#=UB#=VIH, VIO=Vss to VCC IOL = 2.1mA IOH = -1.0mA
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DC Operating Characteristics
4M Version F
Typ (Note)
Item
Symbol
Test Conditions Cycle time=1s, 100% duty, IIO=0mA, CS1# 0.2V, CS2 VCC-0.2V, BYTE#=VSS or VCC, VIN 0.2V or VIN VCC-0.2V, LB# 0.2V or/and UB# 0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL, CS2=VIH, BYTE# = VSS or VCC, VIN=VIL or VIH, LB# 0.2V or/ and UB# 0.2V
Min
Max
Unit
ICC1 Average operating current ICC2
-
-
3
mA
-
-
22
mA
Standby Current (CMOS)
CS1# VCC-0.2V, CS2 VCC-0.2V (CS1# controlled) ISB1 or CS2 0.2V (CS2 controlled), BYTE# = V or V , SS CC (Note) Other input =0~VCC
-
1.0 (Note)
10
A
Note: Typical values are not 100% tested.
DC Operating Characteristics
4M Version G
Typ (Note)
Item
Symbol
Test Conditions Cycle time=1s, 100% duty, IIO=0mA, CS1# 0.2V, CS2 VCC-0.2V, BYTE#=VSS or VCC, VIN 0.2V or VIN VCC-0.2V, LB# 0.2V or/and UB# 0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL, CS2=VIH, BYTE# = VSS or VCC, VIN=VIL or VIH, LB# 0.2V or/ and UB# 0.2V
Min
Max
Unit
ICC1 Average operating current ICC2
-
-
4
mA
-
-
22
mA
Standby Current (CMOS)
CS1# VCC-0.2V, CS2 VCC-0.2V (CS1# controlled) ISB1 or CS2 0.2V (CS2 controlled), BYTE# = V or V , SS CC (Note) Other input = 0~VCC
-
3.0 (Note)
10
A
Note: Typical values are not 100% tested.
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SRAM_Type01_02A0 June 15, 2004
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DC Operating Characteristics
8M Version C
Typ (Note)
Item
Symbol
Test Conditions Cycle time=1s, 100% duty, IIO=0mA, CS1# 0.2V, CS2 VCC-0.2V, BYTE#=VSS or VCC, VIN 0.2V or VIN VCC-0.2V, LB# 0.2V or/and UB# 0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL, CS2=VIH, BYTE# = VSS or VCC, VIN=VIL or VIH, LB# 0.2V or/ and UB# 0.2V
Min
Max
Unit
ICC1 Average operating current ICC2
-
-
3
mA
-
-
22
mA
Standby Current (CMOS)
CS1# VCC-0.2V, CS2 VCC-0.2V (CS1# controlled) ISB1 or CS2 0.2V (CS2 controlled), BYTE# = V or V , SS CC (Note) Other input = 0~VCC
-
-
15
A
Note: Typical values are not 100% tested.
DC Operating Characteristics
8M Version D
Typ (Note)
Item
Symbol
Test Conditions Cycle time=1s, 100% duty, IIO=0mA, CS1# 0.2V, CS2 VCC-0.2V, BYTE#=VSS or VCC, VIN 0.2V or VIN VCC-0.2V, LB# 0.2V or/and UB# 0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1# = VIL, CS2=VIH, BYTE# = VSS or VCC, VIN=VIL or VIH, LB# 0.2V or/ and UB# 0.2V
Min
Max
Unit
ICC1 Average operating current ICC2
-
-
TBD
mA
-
-
TBD
mA
Standby Current (CMOS)
CS1# VCC-0.2V, CS2 VCC-0.2V (CS1# controlled) ISB1 or CS2 0.2V (CS2 controlled), BYTE# = V or V , SS CC (Note) Other input = 0~VCC
-
-
TBD
A
Note: Typical values are not 100% tested.
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SRAM
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AC Operating Conditions
Test Conditions
Test Load and Test Input/Output Reference
Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See Figure 79): CL= 30pF+1TTL
VTM (note 3) R2 (note 2)
CL (note 1)
R1 (note 2)
Figure 79.
Notes:
1. Including scope and jig capacitance. 2. R1=3070, R2=3150. 3. VTM =2.8V.
AC Output Load
AC Characteristics
Read/Write Characteristics (VCC=2.7-3.3V)
Speed Bins 70ns Parameter List Read cycle time Address access time Chip select to output Output enable to valid output LB#, UB# Access Time Read Chip select to low-Z output LB#, UB# enable to low-Z output Output enable to low-Z output Chip disable to high-Z output UB#, LB# disable to high-Z output Output disable to high-Z output Output hold from address change Symbol tRC tAA tCO1, tCO2 tOE tBA tLZ1, tLZ2 tBLZ tOLZ tHZ1, tHZ2 tBHZ tOHZ tOH Min 70 10 10 5 0 0 0 10 Max 70 70 35 70 25 25 25 Units ns ns ns ns ns ns ns ns ns ns ns ns
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Speed Bins 70ns Parameter List Write cycle time Chip select to end of write Address set-up time Address valid to end of write LB#, UB# valid to end of write Write Write pulse width Write recovery time Write to output high-Z Data to write time overlap Data hold from write time End write to output low-Z Symbol tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW Min 70 60 0 60 60 50 0 0 30 0 5 Max 20 Units ns ns ns ns ns ns ns ns ns ns ns
Data Retention Characteristics (4M Version F)
Item VCC for data retention Data retention current Data retention set-up time Recovery time
Notes:
1. CS1 controlled:CS1# VCC-0.2V. CS2 controlled: CS2 0.2V. 2. Typical values are not 100% tested.
Symbol VDR IDR tSDR tRDR
Test Condition CS1# VCC-0.2V (Note 1), VIN 0V. BYTE# = VSS or VCC VCC=3.0V, CS1# VCC-0.2V (Note 1), VIN 0V See data retention waveform
Min 1.5 0 tRC
Typ 1.0 (Note 2) -
Max 3.3 10 -
Unit V A ns
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Data Retention Characteristics (4M Version G)
Item VCC for data retention Data retention current Data retention set-up time Recovery time Symbol VDR IDR tSDR tRDR Test Condition CS1# VCC-0.2V (Note 1), VIN 0V. BYTE# = VSS or VCC VCC=1.5V, CS1# VCC-0.2V (Note 1), VIN 0V See data retention waveform Min 1.5 0 tRC Typ Max 3.3 3 Unit V A ns
Notes: 1. CS1 controlled:CS1# VCC-0.2V. CS2 controlled: CS2 0.2V.
Data Retention Characteristics (8M Version C)
Item VCC for data retention Data retention current Data retention set-up time Recovery time
Notes:
1. CS1 controlled:CS1# VCC-0.2V. CS2 controlled: CS2 0.2V.
Symbol VDR IDR tSDR tRDR
Test Condition CS1# VCC-0.2V (Note 1). BYTE# = VSS or VCC VCC=3.0V, CS1# VCC-0.2V (Note 1) See data retention waveform
Min 1.5 0 tRC
Typ -
Max 3.3 15 -
Unit V A ns
Data Retention Characteristics (8M Version D)
Item VCC for data retention Data retention current Data retention set-up time Recovery time
Notes:
1. CS1 controlled:CS1# VCC-0.2V. CS2 controlled: CS2 0.2V.
Symbol VDR IDR tSDR tRDR
Test Condition CS1# VCC-0.2V (Note 1), BYTE# = VSS or VCC VCC=3.0V, CS1# VCC-0.2V (Note 1) See data retention waveform
Min 1.5 0 tRC
Typ -
Max 3.3 TBD -
Unit V A ns
Timing Diagrams
tRC
Address
tOH tAA
Data Out
Previous Data Valid
Data Valid
Figure 80.
Timing Waveform of Read Cycle(1) (Address Controlled, CS#1=OE#=VIL, CS2=WE#=VIH, UB# and/or LB#=VIL)
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SRAM_Type01_02A0 June 15, 2004
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tRC
Address
tAA tCO1 tOH
CS1#
CS2
tCO2 tBA tHZ
UB#, LB#
OE#
tOLZ tBLZ tLZ
tOE
tBHZ
tOHZ
Data Valid
Data out
High-Z
Notes:
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection.
Figure 81.
Timing Waveform of Read Cycle(2) (WE#=VIH, if BYTE# is Low, Ignore UB#/LB# Timing)
tWC
Address
tCW(2)
CS1#
tWR(4)
tAW
CS2
tCW(2) tBW
UB#, LB#
tWP(1)
WE#
tAS(3)
Data in
tDW
Data Valid
tDH High-Z tOW
High-Z tWHZ
Data out
Data Undefined
Figure 82.
Timing Waveform of Write Cycle(1) (WE# controlled, if BYTE# is Low, Ignore UB#/LB# Timing)
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SRAM
161
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tWC
Address
tAS(3)
CS1#
tCW(2)
tWR(4)
tAW
CS2
UB#, LB#
tBW tWP(1)
WE#
tDW
Data in Data Valid
tDH
Data out
High-Z
High-Z
Figure 83.
Timing Waveform of Write Cycle(2) (CS# controlled, if BYTE# is Low, Ignore UB#/LB# Timing)
tWC
Address
tCW(2)
CS1#
tWR(4)
tAW
CS2
tCW(2) tBW tAS(3) tWP(1)
UB#, LB#
WE#
tDW
Data in Data Valid
tDH
Data out
High-Z
High-Z
Notes: 1. A write occurs during the overlap (tWP) of low CS1# and low WE#. A write begins when CS1# goes low and WE# goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS1# going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS1# or WE# going high.
Figure 84.
Timing Waveform of Write Cycle(3) (UB#, LB# controlled)
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CS1# Controlled VCC 2.7V
tSDR
Data Retention Mode
tRDR
2.2V VDR CS1# GND CS2 Controlled VCC 2.7V CS2
tSDR tRDR
CS1# VCC - 0.2V
Data Retention Mode
VDR 0.4V GND CS2 0.2V
Figure 85.
Data Retention Waveform
June 15, 2004 SRAM_Type01_02A0
SRAM
163
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Information
pSRAM Type 1
4Mbit (256K Word x 16-bit) 8Mbit (512K Word x 16-bit) 16Mbit (1M Word x 16-bit) 32Mbit (2M Word x 16-bit) 64Mbit (4M Word x 16-bit) Features
Fast Cycle Times -- TACC < 70 nS -- TACC < 65 nS -- TACC < 60 nS -- TACC < 55 nS Very low standby current -- ISB < 120 A (64M and 32M) -- ISB < 100 A (16M) Very low operating current -- Icc < 25mA
Functional Description
Mode Read (word) Read (lower byte) Read (upper byte) Write (word) Write (lower byte) Write (upper byte) Outputs disabled Standby Deep power down CE# L L L L L L L H H CE2/ZZ# H H H H H H H H L OE# L L L X X X H X X WE# H H H L L L H X X UB# L H L L H L X X X LB# L L H L L H X X X Addresses X X X X X X X X X I/O 1-8 Dout Dout High-Z Din Din Invalid High-Z High-Z High-Z I/O 9-16 Dout High-Z Dout Din Invalid Din High-Z High-Z High-Z Power IACTIVE IACTIVE IACTIVE IACTIVE IACTIVE IACTIVE IACTIVE ISTANDBY IDEEP SLEEP
Absolute Maximum Ratings
Item Voltage on any pin relative to VSS Voltage on VCC relative to VSS Power dissipation Storage temperature Operating temperature Symbol Vin, Vout VCC PD TSTG TA Ratings -0.2 to VCC +0.3 -0.2 to 3.6 1 -55 to 150 -25 to 85 Units V V W C C
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DC Characteristics (4Mb pSRAM Asynchronous)
Asynchronous Performance Grade Density Symbol VCC VIH VIL IIL ILO Parameter Power Supply Input High Level Input Low Level Input Leakage Current Output Leakage Current Vin = 0 to VCC OE = VIH or Chip Disabled IOH = -1.0 mA VOH Output High Voltage IOH = -0.2 mA IOH = -0.5 mA IOL = 2.0 mA VOL Output Low Voltage IOL = 0.2 mA IOL = 0.5 mA IACTIVE Operating Current Standby Current Deep Power Down Current 1/4 Array PAR Current 1/2 Array PAR Current VCC = 3.3 V VCC = 3.0 V VCC = 3.3 V x x x 25 70 mA 0.2 V 0.8 Vccq V Conditions Min 2.7 1.4 Vccq -0.3 -70 4Mb pSRAM Max 3.3 VCC + 0.3 0.4 0.5 0.5 Units V V V A A
ISTANDBY IDEEP
SLEEP
A
A A A
IPAR 1/4 IPAR 1/2
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DC Characteristics (8Mb pSRAM Asynchronous)
Asynchronous Version Performance Grade Density Symbol VCC VIH VIL IIL ILO Parameter Power Supply Input High Level Input Low Level Input Leakage Current Output Leakage Current Vin = 0 to VCC OE = VIH or Chip Disabled IOH = -1.0 mA VCC-0.4 VOH Output High Voltage IOH = -0.2 mA IOH = -0.5 mA IOL = 2.0 mA VOL Output Low Voltage IOL = 0.2 mA IOL = 0.5 mA IACTIVE Operating Current VCC = 3.3 V VCC = 3.0 V VCC = 3.3 V x x x 25 60 mA A 23 60 mA A 25 60 mA A 0.4 V 0.4 V 0.2 V V Conditions Min 2.7 2.2 -0.3 -55 8Mb pSRAM Max 3.3 VCC + 0.3 0.6 0.5 0.5 Units V V V A A VCC-0.4 V 0.8 VCCQ V Min 2.7 2.2 -0.3 B -70 8Mb pSRAM Max 3.6 VCC + 0.3 0.6 0.5 0.5 Units V V V A A Min 2.7 1.4 -0.3 C -70 8Mb pSRAM Max 3.3 VCC+0.3 0.4 0.5 0.5 Units V V V A A
ISTANDBY Standby Current IDEEP
SLEEP
Deep Power Down Current 1/4 Array PAR Current 1/2 Array PAR Current
A A A
x x x
A A A
x x x
A A A
IPAR 1/4 IPAR 1/2
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DC Characteristics (16Mb pSRAM Asynchronous)
Asynchronous Performance Grade Density Symbol VCC VIH VIL IIL ILO Parameter Power Supply Input High Level Input Low Level Input Leakage Current Output Leakage Current Vin = 0 to VCC OE = VIH or Chip Disabled IOH = -1.0 mA VOH Output High Voltage IOH = -0.2 mA IOH = -0.5 mA IOL = 2.0 mA VOL Output Low Voltage IOL = 0.2 mA IOL = 0.5 mA IACTIVE ISTANDBY IDEEP SLEEP IPAR 1/4 IPAR 1/2 Operating Current Standby Current Deep Power Down Current 1/4 Array PAR Current 1/2 Array PAR Current VCC = 3.3 V VCC = 3.0 V VCC = 3.3 V x x x 25 100 mA A A A A 23 100 mA A A A A 0.4 V 0.4 V VCC-0.4 V Conditions -55 16Mb pSRAM Minimum 2.7 2.2 -0.3 Maximum 3.6 VCC + 0.3 0.6 0.5 0.5 Units V V V A A VCC-0.4 V -70 16Mb pSRAM Minimum 2.7 2.2 -0.3 Maximum 3.6 VCC + 0.3 0.6 0.5 0.5 Units V V V A A
x x x
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DC Characteristics (16Mb pSRAM Page Mode)
Page Mode Performance Grade Density Symbol VCC VIH VIL IIL Parameter Power Supply Input High Level Input Low Level Input Leakage Current Output Leakage Current Vin = 0 to VCC OE = VIH or Chip Disabled IOH = -1.0 mA VOH Output High Voltage IOH = -0.2 mA IOH = -0.5 mA 0.8 Vccq IOL = 2.0 mA VOL Output Low Voltage IOL = 0.2 mA IOL = 0.5 mA IACTIVE Operating Current Standby Current Deep Power Down Current 1/4 Array PAR Current 1/2 Array PAR Current VCC = 3.3 V VCC = 3.0 V VCC = 3.3 V 100 10 65 80 0.2 Vccq 25 mA V 0.2 Vccq 25 mA V 0.2 Vccq 25 mA V V 0.8 Vccq V 0.8 Vccq V Conditions Min 2.7 0.8 Vccq -0.2 -60 16Mb pSRAM Max 3.3 VCC + 0.2 0.2 Vccq 1 Units V V V A Min 2.7 0.8 Vccq -0.2 -65 16Mb pSRAM Max 3.3 VCC + 0.2 0.2 Vccq 1 Units V V V A Min 2.7 0.8 Vccq -0.2 -70 16Mb pSRAM Max 3.3 VCC + 0.2 0.2 Vccq 1 Units V V V A
ILO
1
A
1
A
1
A
ISTANDBY IDEEP
SLEEP
A
100 10 65 80
A
100 10 65 80
A
A A A
A A A
A A A
IPAR 1/4 IPAR 1/2
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DC Characteristics (32Mb pSRAM Page Mode)
Page Mode Version Performance Grade Density Symbol VCC Parameter Power Supply Input High Level Input Low Level Input Leakage Current Output Leakage Current Vin = 0 to VCC Conditions C -65 32Mb pSRAM Min 2.7 Max 3.6 VCC + 0.2 0.4 Units V -60 32Mb pSRAM Min 2.7 Max 3.3 VCC + 0.2 0.2 Vccq 1 Units V E -65 32Mb pSRAM Min 2.7 Max 3.3 VCC + 0.2 0.2 Vccq 1 Units V -70 32Mb pSRAM Min 2.7 0.8 Vccq -0.2 Max 3.3 VCC + 0.2 0.2 Vccq 1 Units V
VIH
1.4
V
0.8 Vccq
V
0.8 Vccq
V
V
VIL
-0.2
V
-0.2
V
-0.2
V
V
IIL
0.5
A
A
A
A
ILO
OE = VIH or Chip Disabled IOH = -1.0 mA
0.5
A
1
A
1
A
1
A
VOH
Output High Voltage
IOH = -0.2 mA IOH = -0.5 mA IOL = 2.0 mA
0.8 Vccq
V 0.8 Vccq
V 0.8 Vccq
V 0.8 Vccq
V
VOL
Output Low Voltage
IOL = 0.2 mA IOL = 0.5 mA
0.2
V 0.2 Vccq
V 0.2 Vccq mA 25
V 0.2 Vccq mA 25
V
IACTIVE
Operating Current Standby Current Deep Power Down Current 1/4 Array PAR Current 1/2 Array PAR Current
VCC = 3.3 V VCC = 3.0 V VCC = 3.3 V
25
mA
25
mA
ISTANDBY
100 10
A
120 10
A
120 10
A
100 10
A
IDEEP
SLEEP
A
A
A
A
IPAR 1/4 IPAR 1/2
65 80
A A
75 90
A A
75 90
A A
65 80
A A
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DC Characteristics (64Mb pSRAM Page Mode)
Page Mode Performance Grade Density Symbol VCC VIH VIL IIL ILO Parameter Power Supply Input High Level Input Low Level Input Leakage Current Output Leakage Current Vin = 0 to VCC OE = VIH or Chip Disabled IOH = -1.0 mA VOH Output High Voltage IOH = -0.2 mA IOH = -0.5 mA IOL = 2.0 mA VOL Output Low Voltage IOL = 0.2 mA IOL = 0.5 mA IACTIVE Operating Current Standby Current Deep Power Down Current 1/4 Array PAR Current 1/2 Array PAR Current VCC = 3.3 V VCC = 3.0 V VCC = 3.3 V 120 10 65 80 0.2 Vccq 25 mA V 0.8 Vccq V Conditions Min 2.7 0.8 Vccq -0.2 -70 64Mb pSRAM Max 3.3 VCC + 0.2 0.2 Vccq 1 1 Units V V V A A
ISTANDBY IDEEP
SLEEP
A
A A A
IPAR 1/4 IPAR 1/2
Timing Test Conditions
Item Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Operating Temperature 0.1 VCC to 0.9 VCC 5ns 0.5 VCC -25C to +85C
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Output Load Circuit
VCC 14.5K I/O 14.5K 30 pF
Output Load
Figure 86. Output Load Circuit
Power Up Sequence
After applying power, maintain a stable power supply for a minimum of 200 s after CE# > VIH.
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AC Characteristics (4Mb pSRAM Page Mode)
Asynchronous Performance Grade Density 3 Volt Symbol trc taa tco toe tba tlz Parameter Read cycle time Address Access Time Chip select to output Output enable to valid output UB#, LB# Access time Chip select to Low-z output UB#, LB# Enable to Low-Z output Output enable to Low-Z output Chip enable to High-Z output UB#, LB# disable to High-Z output Output disable to High-Z output Output hold from Address Change 10 10 5 0 20 Min 70 70 70 20 70 -70 4Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns
Read
tblz tolz thz
tbhz
0
20
ns
tohz toh
0 10
20
ns ns
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Asynchronous Performance Grade Density 3 Volt Symbol twc tcw tas taw tbw twp Parameter Write cycle time Chipselect to end of write Address set up Time Address valid to end of write UB#, LB# valid to end of write Write pulse width Write recovery time Write to output High-Z Data to write time overlap Data hold from write time End write to output Low-Z Write high pulse width 25 0 5 7.5 ns Min 70 70 0 70 70 55 0 20 -70 4Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns ns
Write
twr twhz tdw tdh tow tow
tpc
Page read cycle Page address access time Page write cycle Chip select high pulse width
x x x x
Other
tpa twpc tcp
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AC Characteristics (8Mb pSRAM Asynchronous)
Asynchronous Version Performance Grade Density 3 Volt Symbol trc taa tco toe tba tlz Parameter Read cycle time Address Access Time Chip select to output Output enable to valid output UB#, LB# Access time Chip select to Low-z output UB#, LB# Enable to Low-Z output Output enable to Low-Z output Chip enable to High-Z output UB#, LB# disable to High-Z output Output disable to High-Z output Output hold from Address Change 5 5 5 0 20 Min 55 55 55 30 55 -55 8Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns 5 5 5 0 25 Min 70 70 70 35 70 B -70 8Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns 10 10 5 0 20 Min 70 70 70 20 70 C -70 8Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns
Read
tblz tolz thz
tbhz
0
20
ns
0
25
ns
0
20
ns
tohz toh
0 10
20
ns ns
0 10
25
ns ns
0 10
20
ns ns
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Asynchronous Version Performance Grade Density 3 Volt Symbol twc tcw tas taw tbw twp Parameter Write cycle time Chip select to end of write Address set up Time Address valid to end of write UB#, LB# valid to end of write Write pulse width Write recovery time Write to output High-Z Data to write time overlap Data hold from write time End write to output Low-Z Write high pulse width 40 0 5 x x ns Min 55 45 0 45 45 45 0 25 -55 8Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns ns 40 0 5 x x ns Min 70 55 0 55 55 55 0 25 ns ns 25 0 5 x x ns B -70 8Mb pSRAM Max Units ns ns ns ns ns ns ns Min 70 70 0 70 70 55 0 20 C -70 8Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns ns
Write
twr twhz tdw tdh tow tow
tpc
Page read cycle Page address access time Page write cycle Chip select high pulse width
x x x x
x x x x
x x x x
Other
tpa twpc tcp
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AC Characteristics (16Mb pSRAM Asynchronous)
Asynchronous Performance Grade Density 3 Volt Symbol trc taa tco toe tba tlz Parameter Read cycle time Address Access Time Chip select to output Output enable to valid output UB#, LB# Access time Chip select to Low-z output UB#, LB# Enable to Low-Z output Output enable to Low-Z output Chip enable to High-Z output UB#, LB# disable to High-Z output Output disable to High-Z output Output hold from Address Change 5 5 5 0 25 Min 55 55 55 30 55 -55 16Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns 5 5 5 0 25 Min 70 70 70 35 70 -70 16Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns
Read
tblz tolz thz
tbhz
0
25
ns
0
25
ns
tohz toh
0 10
25
ns ns
0 10
25
ns ns
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Asynchronous Performance Grade Density 3 Volt Symbol twc tcw tas taw tbw twp Parameter Write cycle time Chipselect to end of write Address set up Time Address valid to end of write UB#, LB# valid to end of write Write pulse width Write recovery time Write to output High-Z Data to write time overlap Data hold from write time End write to output Low-Z Write high pulse width 25 0 5 x x ns Min 55 50 0 50 50 50 0 25 -55 16Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns ns 25 0 5 x x ns Min 70 55 0 55 55 55 0 25 -70 16Mb pSRAM Max Units ns ns ns ns ns ns ns ns ns ns
Write
twr twhz tdw tdh tow tow
tpc
Page read cycle Page address access time Page write cycle Chip select high pulse width
x x x x
x x x x
Other
tpa twpc tcp
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AC Characteristics (16Mb pSRAM Page Mode)
Page Mode Performance Grade Density 3 Volt Symbol trc taa tco toe tba tlz Parameter Read cycle time Address Access Time Chip select to output Output enable to valid output UB#, LB# Access time Chip select to Low-z output UB#, LB# Enable to Low-Z output Output enable to Low-Z output Chip enable to High-Z output UB#, LB# disable to High-Z output Output disable to High-Z output Output hold from Address Change 10 10 5 0 5 Min 60 -60 16Mb pSRAM Max 20k 60 60 25 60 Units ns ns ns ns ns ns ns ns ns 10 10 5 0 5 Min 65 -65 16Mb pSRAM Max 20k 65 65 25 65 Units ns ns ns ns ns ns ns ns ns 10 10 5 0 5 Min 70 -70 16Mb pSRAM Max 20k 70 70 25 70 Units ns ns ns ns ns ns ns ns ns
Read
tblz tolz thz
tbhz
0
5
ns
0
5
ns
0
5
ns
tohz toh
0 5
5
ns ns
0 5
5
ns ns
0 5
5
ns ns
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Page Mode Performance Grade Density 3 Volt Symbol twc tcw tas taw tbw twp Parameter Write cycle time Chipselect to end of write Address set up Time Address valid to end of write UB#, LB# valid to end of write Write pulse width Write recovery time Write to output High-Z Data to write time overlap Data hold from write time End write to output Low-Z Write high pulse width 20 0 5 7.5 ns Min 60 50 0 50 50 50 0 5 -60 16Mb pSRAM Max 20k Units ns ns ns ns ns ns ns ns ns ns 20 0 5 7.5 ns Min 65 60 0 60 60 50 0 5 -65 16Mb pSRAM Max 20k Units ns ns ns ns ns ns ns ns ns ns 20 0 5 7.5 ns Min 70 60 0 60 60 50 0 5 -70 16Mb pSRAM Max 20k Units ns ns ns ns ns ns ns ns ns ns
Write
twr twhz tdw tdh tow tow
tpc
Page read cycle Page address access time Page write cycle Chip select high pulse width
25
20k 25
ns ns ns ns
25
20k 25
ns ns ns ns
25
20k 25
ns ns ns ns
Other
tpa twpc tcp
25 10
20k
25 10
20k
25 10
20k
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AC Characteristics (32Mb pSRAM Page Mode)
Page Mode Version Performance Grade Density 3 Volt Symbol trc taa tco toe tba tlz Parameter Read cycle time Address Access Time Chip select to output Output enable to valid output UB#, LB# Access time Chip select to Low-z output UB#, LB# Enable to Low-Z output Output enable to Low-Z output Chip enable to High-Z output UB#, LB# disable to High-Z output Output disable to High-Z output Output hold from Address Change 10 10 5 0 20 C -65 32Mb pSRAM Min 65 Max 20k 65 65 20 65 Units ns ns ns ns ns ns ns ns ns 10 10 5 0 5 -60 32Mb pSRAM Min 60 Max 20k 60 60 25 60 Units ns ns ns ns ns ns ns ns ns 10 10 5 0 5 E -65 32Mb pSRAM Min 65 Max 20k 65 65 25 65 Units ns ns ns ns ns ns ns ns ns 10 10 5 0 5 -70 32Mb pSRAM Min 70 Max 20k 70 70 25 70 Units ns ns ns ns ns ns ns ns ns
Read
tblz tolz thz
tbhz
0
20
ns
0
5
ns
0
5
ns
0
5
ns
tohz toh
0 5
20
ns ns
0 5
5
ns ns
0 5
5
ns ns
0 5
5
ns ns
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Page Mode Version Performance Grade Density 3 Volt Symbol twc tcw tas taw tbw twp Parameter Write cycle time Chipselect to end of write Address set up Time Address valid to end of write UB#, LB# valid to end of write Write pulse width Write recovery time Write to output High-Z Data to write time overlap Data hold from write time End write to output Low-Z Write high pulse width 25 0 5 7.5 ns C -65 32Mb pSRAM Min 65 55 0 55 55 55 0 5 20k Max 20k Units ns ns ns ns ns ns ns ns ns ns 20 0 5 7.5 ns -60 32Mb pSRAM Min 60 50 0 50 50 50 0 5 Max 20k Units ns ns ns ns ns ns ns ns ns ns 20 0 5 7.5 ns E -65 32Mb pSRAM Min 65 60 0 60 60 50 0 5 Max 20k Units ns ns ns ns ns ns ns ns ns ns 20 0 5 7.5 ns -70 32Mb pSRAM Min 70 60 0 60 60 50 0 5 Max 20k Units ns ns ns ns ns ns ns ns ns ns
Write
twr twhz tdw tdh tow tow
tpc
Page read cycle Page address access time Page write cycle Chip select high pulse width
25
20k 25
ns ns ns ns
25
20k 25
ns ns ns ns
25
20k 25
ns ns ns ns
25
20k 25
ns ns ns ns
Other
tpa twpc tcp
25 10
20k
25 10
20k
25 10
20k
25 10
20k
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AC Characteristics (64Mb pSRAM Page Mode)
Page Mode Performance Grade Density 3 Volt Symbol trc taa tco toe tba tlz Parameter Read cycle time Address Access Time Chip select to output Output enable to valid output UB#, LB# Access time Chip select to Low-z output UB#, LB# Enable to Low-Z output Output enable to Low-Z output Chip enable to High-Z output UB#, LB# disable to High-Z output Output disable to High-Z output Output hold from Address Change 10 10 5 0 5 Min 70 -70 64Mb pSRAM Max 20k 70 70 25 70 Units ns ns ns ns ns ns ns ns ns
Read
tblz tolz thz
tbhz
0
5
ns
tohz toh
0 5
5
ns ns
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Page Mode Performance Grade Density 3 Volt Symbol twc tcw tas taw tbw twp Parameter Write cycle time Chipselect to end of write Address set up Time Address valid to end of write UB#, LB# valid to end of write Write pulse width Write recovery time Write to output High-Z Data to write time overlap Data hold from write time End write to output Low-Z Write high pulse width 20 0 5 7.5 ns Min 70 60 0 60 60 50 0 5 20k -70 64Mb pSRAM Max 20k Units ns ns ns ns ns ns ns ns ns ns
Write
twr twhz tdw tdh tow tow
tpc
Page read cycle Page address access time Page write cycle Chip select high pulse width
20
20k 20
ns ns ns ns
Other
tpa twpc tcp
20 10
20k
Timing Diagrams
Read Cycle
tRC Address tAA tOH
Data Out
Previous Data Valid
Data Valid
Figure 87. June 8, 2004 pSRAM_Type01_12_A0
Timing of Read Cycle (CE# = OE# = VIL, WE# = ZZ# = VIH) pSRAM Type 1 183
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tRC Address
tAA
CE# tCO tLZ tOE OE# tOLZ tLB, tUB LB#, UB# tBLZ Data Out High-Z
Figure 88.
tHZ
tOHZ
tBHZ Data Valid
Timing Waveform of Read Cycle (WE# = ZZ# = VIH)
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tPGMAX Page Address (A4 - A20) tRC tPC
Word Address (A0 - A3) tAA CE#
tPA
tHZ
tCO tOE OE# tOLZ LB#, UB# tLB, tUB tBHZ tOHZ
Data Out
Figure 89.
High-Z
tBLZ,
Timing Waveform of Page Mode Read Cycle (WE# = ZZ# = VIH)
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Write Cycle
tWC
Addr es s
tAW
CE#
tWR
tCW tBW
LB#, UB#
tAS
WE#
tWP
tDW High-Z
Dat a In
tDH
Data Valid tWHZ High-Z tOW
Da ta Out
Figure 90.
Timing Waveform of Write Cycle (WE# Control, ZZ# = VIH)
tWC
Ad dres s
tAW
CE#
tWR tAS tBW tCW
LB#, UB#
tWP
WE#
tDW
Dat a In
tDH
Data Valid tWHZ
Da ta O ut
High-Z
Figure 91. Timing Waveform of Write Cycle (CE# Control, ZZ# = VIH) pSRAM Type 1 pSRAM_Type01_12_A0 June 8, 2004
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tPGMAX
Page A ddr es s (A4 - A 20)
tWC
Wor d A ddr es s (A0 - A3 )
tPWC
tAS tCW
CE#
tWP
WE#
tLBW, tUBW
LB#, UB#
tDW High-Z
Dat a Out
tDH
tPDW
tPDH
tPDW
tPDH
Figure 92.
Timing Waveform of Page Mode Write Cycle (ZZ# = VIH)
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Power Savings Modes (For 16M Page Mode, 32M and 64M Only)
There are several power savings modes. Partial Array Self Refresh Temperature Compensated Refresh (64M) Deep Sleep Mode Reduced Memory Size (32M, 16M) The operation of the power saving modes ins controlled by the settings of bits contained in the Mode Register. This definition of the Mode Register is shown in Figure 93 and the various bits are used to enable and disable the various low power modes as well as enabling Page Mode operation. The Mode Register is set by using the timings defined in Figure xxx.
Partial Array Self Refresh (PAR)
In this mode of operation, the internal refresh operation can be restricted to a 16Mb, 32Mb, or 48Mb portion of the array. The array partition to be refreshed is determined by the respective bit settings in the Mode Register. The register settings for the PASR operation are defined in Table xxx. In this PASR mode, when ZZ# is active low, only the portion of the array that is set in the register is refreshed. The data in the remainder of the array will be lost. The PASR operation mode is only available during standby time (ZZ# low) and once ZZ# is returned high, the device resumes full array refresh. All future PASR cycles will use the contents of the Mode Register that has been previously set. To change the address space of the PASR mode, the Mode Register must be reset using the previously defined procedures. For PASR to be activated, the register bit, A4Must be set to a one (1) value, "PASR Enabled". If this is the case, PASR will be activated 10 s after ZZ# is brought low. If the A4 register bit is set equal to zero (0), PASR will not be activated.
Temperature Compensated Refresh (for 64Mb)
In this mode of operation, the internal refresh rate can be optimized for the operation temperature used and this can then lower standby current. The DRAM array in the PSRAM must be refreshed internally on a regular basis. At higher temperatures, the DRAM cell must be refreshed more often than at lower temperatures. By setting the temperature of operation in the Mode Register, this refresh rate can be optimized to yield the lowest standby current at the given operating temperature. There are four different temperature settings that can be programmed in to the PSRAM. These are defined in Figure 93.
Deep Sleep Mode
In this mode of operation, the internal refresh is turned off and all data integrity of the array is lost. Deep Sleep is entered by bringing ZZ# low with the A4 register bit set to a zero (0), "Deep Sleep Enabled". If this is the case, Deep Sleep will be entered 10 s after ZZ# is brought low. The device will remain in this mode as long as ZZ# remains low. If the A4 register bit is set equal to one (1), Deep Sleep will not be activated.
Reduced Memory Size (for 32M and 16M)
In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb device. The mode and array size are determined by the settings in the VA register. The VA register is set according to the following timings and the bit settings in the table "Address Patterns for RMS". The RMS mode is enabled at the time of ZZ
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transitioning high and the mode remains active until the register is updated. To return to the full 32Mb address space, the VA register must be reset using the previously defined procedures. While operating in the RMS mode, the unselected portion of the array may not be used.
Other Mode Register Settings (for 64M)
The Page Mode operation can also be enabled and disabled using the Mode Register. Register bit A7 controls the operation of Page Mode and setting this bit to a one (1), enables Page Mode. If the register bit A7 is set to a zero (0), Page Mode operation is disabled.
64 Mb
32 Mb / 16 Mb
A21 - A8
A7
A6
A5
A4
A3
A2
A1
A0
Reserved Must set to all 0
Temp Compensated Refresh 1 0 0 1 0 = 15oC 1 = 45oC 0 = 70oC 1 = 85oC (default)
Array Mode for ZZ# 0 = PAR (default) 1 = RMS 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 PAR Section 1 = Top 1/4 array 0 = Top 1/2 array 1 = Top 3/4 array 0 = No PAR 1 = Bottom 1/4 array 0 = Bottom 1/2 array 1 = Bottom 3/4 array 0 = Full array (default)
Page Mode 0 = Page Mode Disabled (default) 1 = Page Mode Enabled Deep Sleep Enable/Disable 0 = Deep Sleep Enabled 1 = Deep Sleep Disabled (default)
Figure 93.
Mode Register
June 8, 2004 pSRAM_Type01_12_A0
pSRAM Type 1
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tWC Address tAS CE# tWP WE# tCDZZ ZZ#
Figure 94. Mode Register Update Timings (UB#, LB#, OE# are Don't Care)
tAW
tWR
tZZWE
tZZMIN ZZ# tCDZZ tR
CE#
Figure 95. Deep Sleep Mode - Entry/Exit Timings
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pSRAM_Type01_12_A0 June 8, 2004
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Mode Register Update and Deep Sleep Timings
Item Chip deselect to ZZ# low ZZ# low to WE# low Write register cycle time Chip enable to end of write Address valid to end of write Write recovery time Address setup time Write pulse width Deep Sleep Pulse Width Deep Sleep Recovery
Notes:
1. Minimum cycle time for writing register is equal to speed grade of product.
Symbol tCDZZ tZZWE tWC tCW tAW tWR tAS tWR tZZMIN tR
Min 5 10 70/85 70/85 70/85 0 0 40 10 150
Max
Unit ns
Note
500
ns ns ns ns ns ns ns s s 1 1 1
Address Patterns for PASR (A4=1) (64M)
A2 1 1 1 1 0 0 0 0 A1 1 1 0 0 1 1 0 0 A0 1 0 1 0 1 0 1 0 Active Section Top quarter of die Top half of die Reserved No PASR Bottom quarter of die Bottom half of die Reserved Full array 000000h-3FFFFFh 4Mb x 16 64Mb None 000000h-0FFFFFh 000000h-1FFFFFh 0 1Mb x 16 2Mb x 16 0 16Mb 32Mb Address Space 300000h-3FFFFFh 200000h-3FFFFFh Size 1Mb x 16 2Mb x 16 Density 16Mb 32Mb
June 8, 2004 pSRAM_Type01_12_A0
pSRAM Type 1
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Deep ICC Characteristics (for 64Mb)
Item Symbol Test Array Partition None PASR Mode Standby Current IPASR VIN = VCC or 0V, Chip Disabled, tA = 85C 1/4 Array 1/2 Array Full Array Typ Max 10 75 90 120 A Unit
Item
Symbol
Max Temperature 15C
Typ
Max 50 60 80 120
Unit
Temperature Compensated Refresh Current
ITCR
45C 70C 85C
A
Item Deep Sleep Current
Symbol IZZ
Test VIN = VCC or 0V, Chip in ZZ# mode, tA = 25C
Typ
Max 10
Unit A
Address Patterns for PAR (A3= 0, A4=1) (32M)
A2 0 0 x 1 1 A1 1 1 0 1 1 A0 1 0 0 1 0 Active Section One-quarter of die One-half of die Full die One-quarter of die One-half of die Address Space 000000h - 07FFFFh 000000h - 0FFFFFh 000000h - 1FFFFFh 180000h - 1FFFFFh 100000h - 1FFFFFh Size 512Kb x 16 1Mb x 16 2Mb x 16 512Kb x 16 1Mb x 16 Density 8Mb 16Mb 32Mb 8Mb 16Mb
Address Patterns for RMS (A3 = 1, A4 = 1) (32M)
A2 0 0 1 1 A1 1 1 1 1 A0 1 0 1 0 Active Section One-quarter of die One-half of die One-quarter of die One-half of die Address Space 000000h - 07FFFFh 000000h - 0FFFFFh 180000h - 1FFFFFh 100000h - 1FFFFFh Size 512Kb x 16 1Mb x 16 512Kb x 16 1Mb x 16 Density 8Mb 16Mb 8Mb 16Mb
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Low Power ICC Characteristics (32M)
Item Symbol Test VIN = VCC or 0V, Chip Disabled, tA= 85 C
o
Array Partition 1/4 Array 1/2 Array 4Mb Device
o
Typ
Max 65 80 40 50 10
Unit A A A A A
PAR Mode Standby Current IPAR
RMS Mode Standby Current IRMSSB Deep Sleep Current IZZ
VIN = VCC or 0V, Chip Disabled, tA= 85 C VIN = VCC or 0V, Chip in ZZ mode, tA= 85oC
8Mb Device
Address Patterns for PAR (A3= 0, A4=1) (16M)
A2 0 0 x 1 1 A1 1 1 0 1 1 A0 1 0 0 1 0 Active Section One-quarter of die One-half of die Full die One-quarter of die One-half of die Address Space 00000h - 0FFFFh 00000h - 7FFFFh 00000h - FFFFFh C0000h - FFFFh 80000h - 1FFFFFh Size 256Kb x 16 512Kb x 16 1Mb x 16 256Kb x 16 512Kb x 16 Density 4Mb 8Mb 162Mb 4Mb 8Mb
Address Patterns for RMS (A3 = 1, A4 = 1) (16M)
A2 0 0 1 1 A1 1 1 1 1 A0 1 0 1 0 Active Section One-quarter of die One-half of die One-quarter of die One-half of die Address Space 00000h - 0FFFFh 00000h - 7FFFFh C0000h - FFFFFh 80000h - FFFFFh Size 256Kb x 16 512Kb x 16 256Kb x 16 512Kb x 16 Density 4Mb 8Mb 4Mb 8Mb
Low Power ICC Characteristics (16M)
Item PAR Mode Standby Current Symbol IPAR Test VIN = VCC or 0V, Chip Disabled, tA= 85 C
o
Array Partition 1/4 Array 1/2 Array 4Mb Device
o
Typ
Max 65 80 40 50 10
Unit A
RMS Mode Standby Current
IRMSSB IZZ
VIN = VCC or 0V, Chip Disabled, tA= 85 C VIN = VCC or 0V, Chip in ZZ# mode, tA= 85oC
8Mb Device
A
Deep Sleep Current
A
June 8, 2004 pSRAM_Type01_12_A0
pSRAM Type 1
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Revision Summary
Revision A (May 3, 2004)
Initial release.
Revision A1 (May 6, 2004)
MCP Features Corrected the high performance access times. Connection Diagrams Added reference points on all diagrams. Ordering Information Corrected package types. Corrected the description of product family to Page Mode Flash memory. pSRAM Type 1 Corrected the description of the 8Mb device to 512Kb Word x 16-bit. pSRAM Type 6 Corrected the description of the 2Mb device to 128Kb Word x 16-bit. Corrected the description of the 4Mb device to 256Kb Word x 16-bit.
Revision A2 (May 11, 2004)
General Description Corrected the tables to reflect accurate device configurations.
Revision A3 (June 16, 2004)
Ordering Information Corrected the Valid Combinations tables to reflect accurate device configurations. SRAM New section added.
Revision A4 (July 16, 2004)
Global Changes
Global Change of FASL to Spansion. Global change to remove space between M and Mb callouts.
"32Mb Flash Memory" on page 2
Replaced "S71PL032J08-07" with "S71PL032J08-0B". Replaced "S71PL032JA0" with "S71PL032JA0-07". Added row with the following content: S71PL032JA0-08; 65; 16Mb pSRAM; 70; pSRAM3; TLC056.
"64Mb Flash Memory" on page 2
Replaced "S71PL064J08-0K" with "S71PL064J08-0B". Replaced "S71PL064J08-0P" with "S71PL064J08-0U". Deleted "S71PL064J80-05" row. Replaced "S71PL064JA0-07" with "S71PL064JA0-0K".
194
Revision Summary
S71PL254/127/064/032J_00_A6 November 22, 2004
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Information
Replaced "S71PL064JA0-0Z" with Added row with the following content:S71PL064JB0-07; 65; 32M pSRAM; 70; Psram 1; TLC056.
"32Mb Flash Memory" on page 2
Replaced "S71PL032JA0-08" with "S71PL032JA0-0F".
"64Mb Flash Memory" on page 2
Replaced "S71PL032JA0-07" with "S71PL032JA0-0K".
"128Mb Flash Memory" on page 3
Added row with the following content: S71PL127JB0-9; 65; 32M pSRAM; 70; pSRAM; TLA064. Replaced "S71PL127JB0-97" with "S71PL127JB0-9Z". Added row with the following content: S71PL127JC0-97; 65; 64M pSRAM; 70; pSRAM1; TLA064. Replaced "S71PL127JC0-9P" with "S71PL127JC0-9Z". In the S71PL254JB0-TB row changed pSRAM type from "pSRAM3" to "pSRAM2".
"256Mb Flash Memory (2xS29PL127J)" on page 3
Added row with the following content: S71PL254JB0-TB; 65; 32M pSRAM; 70; pSRAM3; FTA084. Added row with the following content: S71PL254JC0-TB; 65; 64M pSRAM; 70; pSRAM2; FTA084.
"Connection Diagram (S71PL127J)" on page 11
Updated pins D8, D9, and L5. Added notes 2 and 3 to drawing.
"Connection Diagram (S71PL254J)" on page 12
Updated pins D8 and D9. Added Note 2 to drawing.
"S71PL032J Valid Combinations" on page 15
Changed S71PL032J08 (p)SRAM Type Access Time (ns) from "SRAM1" to "SRAM2" (4 changes made in table). Changed S71PL032JA0 (p)SRAM Type Access Time (ns) from "SRAM3 / 70" to pSRAM3 /70". Deleted all cells with the following collaborated text: "BAW,BFW, BAI. BFI". Merged previous place holder with cell above.
"S71PL064J Valid Combinations" on page 16
In (p)SRAM Type/Access Time (ns) changed all instances of "stet" to "pSRAM1/ 70". In Package Modifier/Model Number changed all instances of "stet" to "07". Added row to BAW Package and Temperature sections with the following content: S71PL064JB0; 07; 65 (previously inclusive); pSRAM1/70.
"S71PL127J Valid Combinations" on page 17
Changed the S71PL127JA0 Package Modifier/Model Number from "9Z" to "9P" (4 instances).
November 22, 2004 S71PL254/127/064/032J_00_A6
Revision Summary
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Information
Added 4 rows with the following content: S71PL127JC0; 97; pSRAM1/70.
"S71PL254J Valid Combinations" on page 18
Added 4 rows with the following content: S71PL254JC0; TB; pSRAM2/70. Added 4 rows with the following content: S71PL254JB0; TB; pSRAM2/70.
"S71PL254/127/064/032J based MCPs" on page 1
Added 254M to Megabit indicator. Added 16 to CMOS indicator.
Revision A5 (September 14, 2004)
Product Selector Guide Updated the 128Mb Flash Memory table. Valid Combinations Table Updated the S71PL127J Valid Combinations table.
Revision A6 (November 22, 2004)
Product Selector Guide Updated the 32Mb and 64Mb tables. Valid Combinations Tables Updated the 32Mb and 64Mb combinations. Physical Dimensions Added the TSB064 package.
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion LLC. Spansion LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion LLC assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright (c) 2004 Spansion LLC. All rights reserved. Spansion, the Spansion logo, MirrorBit, combinations thereof, and ExpressFlash are trademarks of Spansion LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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Revision Summary
S71PL254/127/064/032J_00_A6 November 22, 2004

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